Hello,
since updating to versions 24.1.4 and now to 24.1.5 LTSpice returns an error when trying to run an operating point simulation on a simple circuit with two MOSFET-s. The returned error message is here:
LTspice 24.1.5 for Windows
Circuit: C:\Users\dce_pc4\Desktop\AIC\01_transistors\tranzistorMOS-psf.net
Start Time: Tue Mar 18 15:33:18 2025
C:\Users\dce_pc4\Desktop\AIC\01_transistors\tranzistorMOS-psf.net(6): Node or model name expected.
Note: A model "p018" is defined, but length (1e-06) and/or width (9e-06) don't match.
Mp N002 N002 N001 N001 p018 l=1u w=9u ad=1.8p as=1.8p pd=18.4u ps=18.4u m=1
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
C:\Users\dce_pc4\Desktop\AIC\01_transistors\tranzistorMOS-psf.net(7): Node or model name expected.
Note: A model "n018" is defined, but length (1e-06) and/or width (4.9999999999999996e-06) don't match.
M1 N003 N003 0 0 n018 l=1u w=5u ad=1p as=1p pd=10.4u ps=10.4u m=1
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
I believe this is a netlist parsing error that might have to do with node naming other users ran into. It has similarities with other threads but I could not apply the suggestions directly to my case. I attached the necessary files in a ZIP archive with and I would appreciate if anyone could take a look.
Thanks,
Gabor
Dear gcsipkes ,
This is model binning in action. Your p018 model defines minimum and maximum widths and lengths that are too strict. Just remove the "lmin", "lmax", "wmin", and "wmax" parameters from the model card.
Best Regards,
Mathias
Thanks Mathias, that solved it. It was just strange that it worked with binning until recent versions.
Gabor