AD8330
Production
The AD8330 is a wideband variable gain amplifier for applications
requiring a fully differential signal path, low noise, well-defined
gain, and moderately...
Datasheet
AD8330 on Analog.com
Hi,
I want to simulate the AD8330 with LTSpice. Therefore i downloaded the SPICE model and created a symbol and schematic as shown below. Unfortunately the simulation fails because "Iteration limit reached". There is an error in the log which states that: "ERROR: Node u1:n662042 is floating and connected to current source u1:G_G2". Maybe something is wrong with my setup? Any help would be appreciated. Ultimately i want to check if a small signal at the input is amplified as i would expect it.
Thanks in advance
PaulCA - Moved from Variable Gain Amplifiers (VGA) to LTspice. Post date updated from Tuesday, March 11, 2025 8:12 AM UTC to Wednesday, March 12, 2025 8:00 AM UTC to reflect the move.
PaulCA - Moved from Variable Gain Amplifiers (VGA) to LTspice. Post date updated from Wednesday, March 12, 2025 8:00 AM UTC to Wednesday, March 12, 2025 8:00 AM UTC to reflect the move.
Hi.
I updated to LTSpice 24.1.5 and the same issue persists.
BR
qojote Will you please attach your simulation files, including the schematic (.asc), symbol (.asy), and model (.cir) files?
Hi. Of course. Please find those files attached. BR
Hello qojote and AnneM,
I have done some simulations on my end, and it looks like the model was able to output the correct output signal level by connecting the OFST pin to GND and by floating the MODE pin (normal operating condition). In my simulation, 500mV is applied to the VDBS pin, which translates to a gain of 16.67dB or 6.8V/V. Multiplying the input voltage of 250mVpk to the Gain, the calculated peak output voltage should be 1.7Vpk, and this is similar to what I have simulated below. But, as can be seen below, there is still an error that says "ERROR: Node u1:n662042 is floating and connected to current source u1:G_G2".