Hello,
I am attempting to perform a worst-case circuit analysis on a design that implements the LT3014HVES5. I have two questions:
- Is the LTspice model accurate for output impedance? I have the following plotted, but no measurement data to correlate to. /resized-image/__size/640x480/__key/communityserver-discussions-components-files/1020/0537.pastedimage1735605013313v1.png
- Is there a straightforward method for tolerancing the output impedance in the model? What bounds can we use and how can we implement them?
Thank you so much!
Jake