Parallel LT8638S Problem Simulating in LTspice with >37V input/output. Real or Model?

Hi SPafi ,

Can you upload your schematic? If you have any custom components, include those, too. Zip everything up and drag to the reply field. I might transfer this question to the LTspice forum for now.

mike

Hi Mike,

I can not upload the whole schematic, but simulating the template at high voltage gives similar behaviour:

I modified this:
https://www.analog.com/media/en/simulation-models/LT8638S.asc
To this, to show the issue:
LT8638S parallel HV.zip

I understood that above 37V the IC disables forced continuous conduction mode (page 17), probably in order to keep Vin from possible boost. But I didn't expect losing sync.

External clock is also ignored by LT8638S if Vin>37V. :-( 

Hi SPafi ,

Got it, thanks, we'll look into it.

mike

Sorry, this was my mistake! External clock does synchronise.

Hi SPafi ,

That does look like a model problem. I'll report it.

Some other things I noticed. At 37.5V, the clock signal will run for a couple of cycles at 37.5V, then stop. At other , lower Vin, it's just a messy signal, as shown in the pic. I don't see anything in the datasheet that suggests some limit on the CLKOUT relative to input voltage. The part looks pretty plug and play, and the tech for producing these clock signals for sync is pretty mature, so I'm sure the part works fine IRL.

For now, for simulation, I would try your suggestion of trying with two external out of phase clocks. You could try the LTC6909 built for this purpose or simply apply a PWM signal to both sync pins. I may give it a shot.

mike

Hi Mike,

Thank you for your fast answer!

It would be nice to know if CLKout realy work IRL, but I will implement complementary ext clk just in case. 

Please update if any news!

Best regards,
Peter

Hi SPafi ,

Since I don't have that part on a bench in front of me, I can't 100% attest to the CLK signal, but I would be very surprised if we released a part with that problem. Assuming the silicon used to produce that particular signal is relatively old tech. A bad model is significantly more likely. I can try to reach out to an apps engineer here to confirm.

I have confirmation that this is a model problem.

mike 

Hi SPafi ,

Since I don't have that part on a bench in front of me, I can't 100% attest to the CLK signal, but I would be very surprised if we released a part with that problem. Assuming the silicon used to produce that particular signal is relatively old tech. A bad model is significantly more likely. I can try to reach out to an apps engineer here to confirm.

I have confirmation that this is a model problem.

mike