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DFlop running into timing issue

Category: Software
Product Number: LTSpice
Software Version: LTSpice v24.0.9

I have the following schematic. But the system cannot do the timing for some reason. Is there something about the setup that i am doing wrong? {Rd} = 1k; {Cd} = 15nF. Both digital devices, Schmitt and DFlop have VHIGH set to 5V. I use the schmitt trigger so the transition is instant so there is no ambiguity on the DFlop CLR input. It does appear like the timing error is happening around when the Schmitt trigger input is ~2.5V. i tried to remove the schmitt trigger and it still fails same error and time. I also tried to pull the CLR to gnd with a 1Ohm resistor and that did not help.

when i run the above circuit i get the following error



Overall i am trying to just have an output of time RC every clock pulse. so wether my clock pulse is 1us or 200us, the output will be high always 25us. this is just a small piece of whole thing though
[edited by: Injanear at 4:53 PM (GMT -5) on 15 Feb 2024]
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