Variable output not coming from frequency divider in PLL circuit

Question

I was simulating a PLL circuit in LTSpice. I implemented frequency divider circuit using XOR gate and 74LS90 BCD counter. I am not getting a time-varying output from the BCD counter. In essence, frequency divider operation is not performed. 
 8585.Draft20.asc

PaulDaria · Accepted Answer

Hi NIT ,

It is missing the LM301 definition. and thus, I cannot run your application circuit. however, for easier frequency divider, there is a component in LTspice known as Counter that can divide the frequency. you need to put Cycles=<divider> as its parameter

Thank you.

Regards,

PaulDaria