Hi,
I’m working on a ADP7182 design.
First there seems to be an Error In the datasheet (Rev. M) on the specifications table on page 4 regarding the Output Noise. Vout should be -15 V instead of -5 V for the for both values in adjustable mode (with and without the noise reduction). The values for the divider at least are the same as on the next page at the PSRR section and at the example on page 25.
Second when I try to simulate the example on page 25 in LTspice the simulated noise does not agree very well with the numbers of the example (I assuming a Bandwidth of 10 Hz – 100 kHz like in the specification table):
Noise w/o NR in example on p. 25: 220 µV rms – LTspice: 266 µV rms – Error 21%
Noise w NR in example on p. 25: 35 µV rms – LTspice: 48 µV rms – Error 39%
Is the LTspice model correct in predicting the noise values?
LTspice circuit:
Results from spice error log:
Best regard
Oliver
