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LTspice, Capacitor "Series Inductance" and HF Spikes [Part II]

Category: Software
Product Number: LT8362
Software Version: 17.0.42 (LTSpice XVII for OS X)

In April 2018, I began running LT8362 SEPIC power supply simulations in LTSpice (for Mac OS X), with a 5V output.  There's a long and detailed discussion about that here. That project was shelved until recently, and I never obtained the approval to buy parts to build an actual working circuit.  The design requirements changed, now calling for a 3.3V output instead of 5.0V. I adjusted the LTSpice simulation file accordingly, which you can download here:

5315.LTSpice_LT8362_SimFile.zip

(Please note that I have still not yet built a working circuit. I am merely simulating in LTSpice for now.)

PROBLEM

Despite it having been 4 years since my last discussion, the newest version of LTSpice (17.0.42 for OS X) is still producing unexpectedly large ESL spikes when I try to more accurately simulate the circuit by adding the appropriate Series Inductance on the output capacitors. (Basically, I am using the Wurth capacitor models, since they include Series Inductance. Not sure why the other capacitor makers don't do that.) With the Series Inductance field left blank on some of my output capacitors, the output simulates as expected.  But once the more accurate capacitor model with Series Inductance is used, I suddenly get large ESL spikes on the output, starting from about 23.317ms.

This power supply will be for automotive use, so I am using the ISO 16750-2 12V Starting Profile, although I've made some adjustments to make it simulate faster as Vin falls (such as starting the voltage at about 7V instead of 12V).

EXAMPLES

More specifically, when all the output capacitors have Series Inductance (like any real capacitor), I am seeing this unexpected output...

Has Series Inductance

That massive blob of blue is comprised of shockingly large 1.5Vp-p ESL spikes on the 3.3V output, despite my use of largely the same ferrite bead EMI filter shown on pages 27 & 28 of the LT8362 datasheet. Load current in my circuit rises to 200mA, which should be well within the capability of the LT8362 and the current design. (It is a SEPIC design, which means the output should remain close to 3.3V even when the input voltage drops a bit below 3.3V.  In this simulation, I allow Vin to drop as low as 2.9V to simulate worst case 12V vehicle cold cranking.)  I also simulated it with a 300mA load, and the ESL spikes are even more massive than the above blue blob.

Below is how the output looks after I delete Series Inductance from C7 (the primary 22uF output capacitor) and from C4 (the INTVcc) capacitor.  (For some reason LTSpice refuses to simulate when I only delete the Series Inductance of C7. I am forced to also delete the Series Inductance of C4 to get it to simulate, which baffles me.  LTSpice bug?  But the example is nevertheless sound, clearly showing that the lack of capacitor Series Inductances prevents occurrence of abnormally large ESL spikes.)

Less Series Inductance

I know the ESL spikes have nothing to do with Anti-resonance pertaining to the output capacitors because I simulated that in a separate file and found the curve to be perfectly fine...

No Anti-resonance

Here's the sim file for the above graph:

0552.LT8362_OutputCapacitor_NoAnti-Resonance.asc.zip

And to prove it's not Anti-resonance, here is the same test (no Series Inductance on C7 or C4), but this time without the ferrite bead and capacitor EMI filter on the output (still no major ESL spikes, although they are 107mVp-p, which is too large for my preference; but a ferrite bead EMI filter cleans that up quite nicely, as shown in the first output graph).

No Ferrite Bead EMI Filter

The problem has nothing to do with R7, the 100kΩ Mode resistor, since the problem results even with SSFM disabled.  The two large input capacitors (330uF each) also have nothing to do with the problem, since the ESL spikes remain even without those two caps. DC Bias on the output capacitors it not the issue either.  I even tried simulating PCB trace resistance by adding 2mΩ of resistance between output capacitors, but that had no effect on the ESL spikes.

While no simulation software is perfect, and while an actual circuit on PCB will determine if a problem exists, I did expect more of LTSpice this go around, now that it's been 4 years+ since my last simulation of a very similar circuit (same switcher IC, just with a different output voltage).

Triangular flag on post I would appreciate hearing your thoughts on whether this ESL spike issue remains a bug in LTSpice, or if there is something in my circuit that I am overlooking which is triggering the large 1.5Vp-p spikes when Series Inductance is used on all of the output capacitors.

Thank you.

P.S. BUG REPORT: There is a crashing bug in LT Spice XVII 17.0.42 for MacOS. To repeat the bug, open my *.asc file (linked earlier in this post), then right-click on the Load (I1), click the "Additional PWL points" button, select the bottommost Time/Value entry, click Delete, click OK, click OK, and then the app will crash.  It happens every single time you try it.



7/7/2022: Added "P.S." Bug Report.
[edited by: KIRAMEK at 7:37 AM (GMT -4) on 7 Jul 2022]
Parents
  • Dear KIRAMEK,

    Your test cases look the way they do not because of LTspice bugs. On the contrary, LTspice is doing exactly as asked. Instead, there are several circuit issues to address here:

    LT8362

    This part has an INTVCC pin. In the macro model, this pin is driven by a very simple regulator (good for speed!), that doesn't work well with caps that have ESL. Thus, I highly recommend you just use an ideal cap here. Rest assured, the real IC is designed to work with real ceramic caps, but there is no benefit in accurately modelling the INTVCC regulator.

    Just adding an ESL to a cap is not an adequate model for the output cap of a switcher. The voltage spikes you see on the output are a direct result of the high di/dt caused by the switcher. A real cap is distributed, which means that the plates further away from the terminals have a higher ESL and therefore carry less current, which increases the resistive losses of the plates closer to the terminals. This adds significant dampening and thus makes the ESR frequency dependent. This detail, which is important for switchers, cannot be modelled by a simple inductor.

    In your case, these current spikes are particularly high because you are using a diode that is too slow. (Excessive reverse recovery time.) The datasheet recommends fast Schottky diodes. Your circuit works just fine with a DFLS260, for example.

    LT8494

    Wrong diode again. If you replace the diode with, for example, an ONSEMI MBRA2H100 as recommended in the datasheet, your circuit runs just fine.

    Best Regards,
    Mathias

  • Thank you for sharing your detailed thoughts. 

    Actually, I was not simulating only "simple inductors" within the capacitor models (which consist of only adding Lser to the capacitor in LTSpice).  I did do that, but I also downloaded more "complex" capacitor models from the capacitor manufacturers and used those with the same bad results (or worse) on the simulated output (i.e., bad results = large peak-to-peak spikes).  For example, as mentioned in my ASC file of the LT8494 above, the two capacitors that are tied to the output by default are not simplistic models with simplistic inductor-only additions. The complexity of the capacitor model in that LT8494 ASC file goes beyond the mere addition of Lser to a capacitor in LTSpice. Here's the spice model I'm talking about...

    * MSASE32YBB5476_TNA01     SPICE MODEL  ( General Type )
    *--------------------------------------------------------------------------------------------------------
    * Model Generated by TAIYO YUDEN Corporation (http://www.ty-top.com)
    * Version 1.0
    * TAIYO YUDEN Control No. 170508_110404
    * Copyright(c) 2012 TAIYO YUDEN CO.,LTD. All Rights Reserved.
    *--------------------------------------------------------------------------------------------------------
    *
    * Product Description (link to TY-COMPAS)
    * https://ds.yuden.co.jp/TYCOMPAS/or/detail?pn=MSASE32YBB5476MTNA01&u=M
    *
    * Products Name : Multilayer Ceramic Capacitors
    *
    * Characteristics :
    *     Capacitance : 47 uF , Rated Voltage : 16V , TCC : X5R
    *     Case Size : 3.2 x 2.5 / 0.126 x 0.098 [mm/inch] , Thickness : 1.9 / 0.075 [mm/inch]
    *     (Conditions: Temperature = 25 degC , DC Bias Current/Voltage = 0A / 0V)
    *
    * Frequency Range : 40Hz - 3GHz
    *
    * External Node Assignments :
    *
    *  1  o---| |---o  2
    *
    *--------------------------------------------------------------------------------------------------------
    .SubCkt MSASE32YBB5476_TNA01 1 2
    ****************************
    C0 1 110 36.27u
    Cm 1 101 6.3112u
    C1 101 102 14.631u
    Rc1 101 102 455.21
    C2 102 103 6.5188u
    Rc2 102 103 78.476
    C3 103 110 8.6148u
    Rc3 103 110 1.5117
    C2m 1 301 2.7333u
    C21 301 302 34.76u
    Rc21 301 302 234.85
    C22 302 303 39.497u
    Rc22 302 303 200.61
    C23 303 304 36.532u
    Rc23 303 304 193.03
    C24 304 305 31.975u
    Rc24 304 305 213.82
    C25 305 306 16.291u
    Rc25 305 306 250.37
    C26 306 307 10.381u
    Rc26 306 307 7.9823
    C27 307 308 6.1305u
    Rc27 307 308 12.703
    C28 308 309 4.0464u
    Rc28 308 309 14.892
    C29 309 110 0.1423u
    Rc29 309 110 1.7544
    Rp0 1 110 2.12765957446809Meg
    L0 110 120 0.14025n
    Lm 120 130 0.4932n
    L1 120 121 0.3125n
    RL1 121 130 0.17412
    L2 120 122 0.79715n
    RL2 122 130 64.954m
    L3 120 123 194.64n
    RL3 123 130 1.6624k
    CR 120 124 11.73u
    LR 124 125 0.44481n
    RR 125 130 9.3678m
    CL 130 140 4.0985p
    LL 130 140 0.14059n
    RL 130 140 12.607
    Rs 140 2 2.3625m
    ****************************
    .ends MSASE32YBB5476_TNA01

    I am also not understanding how the Super Barrier Diode (SBR) I am using is somehow slower than a Schottky.  Generally, SBRs should be comparable to Schottky diodes in terms of switching performance and Trr. 

    Why did I choose an SBR over a Schottky?  Because the switcher IC datasheets say plainly that the lower the Vf the better, and SBRs have even lower Vf than standard Schottky diodes, yet with the same fast switching speed. 

    As such, if you could explain in detail why an SBR is bad for switching power supply use, I would appreciate hearing it. 

    With that said, it is interesting that the noise on the simulated output is reduced (only when the ferrite bead filter is retained) when using the ONSEMI MBRA2H100, as compared with the SBR2U60S1F that I choose in my original ASC file.  That is something I don't fully understand in light of what I said about SBR's being the same in terms of switching speed as a Schottky, yet with the SBR having a lower Vf (and therefore having the potential to beat a Schottky in these switch mode designs).  Perhaps the SBR spice model for SBR2U60S1F isn't optimized?  Regardless, here are the output graphs from my modified LT8362 simulation...

    With MBRA2H100 & Bead (Lser retained in capacitors):

    With Bead

    With MBRA2H100 but without Bead (Lser retained in capacitors):

    Without Bead

    Since LTSpice unfortunately does not have a built-in model for the ONSEMI MBRA2H100, I had to download it from the manufacturer.  More specifically, I visited the MBRA2H100 web page here, which in turn allows me to find the Spice Model page here. Not knowing which SPICE version is best, I downloaded and used the Spice3 Model (from that same web page). I added the text content of that model to the page via Spice directive, and my ASC file for that is here...

    LT8362_SEPIC_Sim_MBRA2H100.asc.zip

    Regardless of diode choice, deleting Lser on a couple of the output capacitors fixes the spikes-on-output problem regardless of the diode.

    I look forward to hearing in additional thoughts you might have in light of this.

    Thank you.

  • As I have already explained, the cap on the INTVCC pin should not have an ESL. That is a model restriction with no practical relevance.

    In general, a cap with a simple ESL is not an adequate model for a real ceramic cap. So don't use it for an SMPS.

    An SBR should be a suitable replacement for a Schottky diode. As for the SBR2U60S1F, I merely observed that it is not fast enough in simulation. Whether or not that's just a model problem, I cannot tell. However, the datasheet is suspiciously vague about its use in an SMPS.

    Best Regards,
    Mathias

  • Thank you for sharing additional thoughts. I appreciate the extra information, especially your agreement about the fact SBR's should be suitable as replacements for standard Schottky diodes.

    Here are a few more findings of mine that pertain to your advice...

    1. When I delete only Lser on C4 (attached to INTVcc on the LT8362), leaving Lser intact on all other capacitors (e.g., C7) and also using the same SBR2U60S1F diodes, there is no change whatsoever on the amplitude of the voltage spikes on the simulated output. That remains true with or without the Bead filter on the output. However, removing Lser on C4 does offer the significant benefit of making the simulation run faster, which is appreciated.

    2. When I swap out the SBR2U60S1F diode for mbrs2h100t3g and retest the LT8362 simulation as described in (1) above (with & without Lser on C4), there is no change whatsoever on the amplitude of the voltage spikes on the simulated output. However, there is significant ringing on the initial voltage ramp of the simulated output when the mbrs is used, as compared to when I am using the SBR.  Based on what I see, the SBR seems to offer a better simulated result when used in my LT8362 ASC file. (I tested this without the Bead filter.)

    3. If I used the SBR diode, delete Lser on C4 and also delete Lser on C7, but leave Lser on all other capacitors, simulation speed is faster and pretty much all voltage spikes on the simulated output are gone, even without the Bead filter.

    4. In my opening post, I am simulating a 3.3V output @200mA, and I used 7.0V as the input voltage.  I got 107mVp-p noise on the simulated output.  If boost the Input voltage to 12V and the output to 5.0V and simulate without Lser on C4 & C7, and without the Bead filter, once V(in) drops to about 2.9V (automotive cold crank), the peak-to-peak noise on the simulated output is about the same. Adding a Bead filter cleans that up, but it's difficult to know from the simulation result if indeed there will be that much noise, and whether a Bead is even needed.

    All said, the key to eliminating those massive voltage spikes on the simulated output in my LT8362 example is completely tied to deleting all Lser on output capacitor C7, and deleting all Lser on C4 improves simulation speed (and may even be required to get the simulation to even run).  Deleting Lser on the two output capacitors of my LT8494 simulation is also the ticket to success with that, even if I use the SBR diode in the simulation.

Reply
  • Thank you for sharing additional thoughts. I appreciate the extra information, especially your agreement about the fact SBR's should be suitable as replacements for standard Schottky diodes.

    Here are a few more findings of mine that pertain to your advice...

    1. When I delete only Lser on C4 (attached to INTVcc on the LT8362), leaving Lser intact on all other capacitors (e.g., C7) and also using the same SBR2U60S1F diodes, there is no change whatsoever on the amplitude of the voltage spikes on the simulated output. That remains true with or without the Bead filter on the output. However, removing Lser on C4 does offer the significant benefit of making the simulation run faster, which is appreciated.

    2. When I swap out the SBR2U60S1F diode for mbrs2h100t3g and retest the LT8362 simulation as described in (1) above (with & without Lser on C4), there is no change whatsoever on the amplitude of the voltage spikes on the simulated output. However, there is significant ringing on the initial voltage ramp of the simulated output when the mbrs is used, as compared to when I am using the SBR.  Based on what I see, the SBR seems to offer a better simulated result when used in my LT8362 ASC file. (I tested this without the Bead filter.)

    3. If I used the SBR diode, delete Lser on C4 and also delete Lser on C7, but leave Lser on all other capacitors, simulation speed is faster and pretty much all voltage spikes on the simulated output are gone, even without the Bead filter.

    4. In my opening post, I am simulating a 3.3V output @200mA, and I used 7.0V as the input voltage.  I got 107mVp-p noise on the simulated output.  If boost the Input voltage to 12V and the output to 5.0V and simulate without Lser on C4 & C7, and without the Bead filter, once V(in) drops to about 2.9V (automotive cold crank), the peak-to-peak noise on the simulated output is about the same. Adding a Bead filter cleans that up, but it's difficult to know from the simulation result if indeed there will be that much noise, and whether a Bead is even needed.

    All said, the key to eliminating those massive voltage spikes on the simulated output in my LT8362 example is completely tied to deleting all Lser on output capacitor C7, and deleting all Lser on C4 improves simulation speed (and may even be required to get the simulation to even run).  Deleting Lser on the two output capacitors of my LT8494 simulation is also the ticket to success with that, even if I use the SBR diode in the simulation.

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