In April 2018, I began running LT8362 SEPIC power supply simulations in LTSpice (for Mac OS X), with a 5V output. There's a long and detailed discussion about that here. That project was shelved until recently, and I never obtained the approval to buy parts to build an actual working circuit. The design requirements changed, now calling for a 3.3V output instead of 5.0V. I adjusted the LTSpice simulation file accordingly, which you can download here:
(Please note that I have still not yet built a working circuit. I am merely simulating in LTSpice for now.)
Despite it having been 4 years since my last discussion, the newest version of LTSpice (17.0.42 for OS X) is still producing unexpectedly large ESL spikes when I try to more accurately simulate the circuit by adding the appropriate Series Inductance on the output capacitors. (Basically, I am using the Wurth capacitor models, since they include Series Inductance. Not sure why the other capacitor makers don't do that.) With the Series Inductance field left blank on some of my output capacitors, the output simulates as expected. But once the more accurate capacitor model with Series Inductance is used, I suddenly get large ESL spikes on the output, starting from about 23.317ms.
This power supply will be for automotive use, so I am using the ISO 16750-2 12V Starting Profile, although I've made some adjustments to make it simulate faster as Vin falls (such as starting the voltage at about 7V instead of 12V).
More specifically, when all the output capacitors have Series Inductance (like any real capacitor), I am seeing this unexpected output...
That massive blob of blue is comprised of shockingly large 1.5Vp-p ESL spikes on the 3.3V output, despite my use of largely the same ferrite bead EMI filter shown on pages 27 & 28 of the LT8362 datasheet. Load current in my circuit rises to 200mA, which should be well within the capability of the LT8362 and the current design. (It is a SEPIC design, which means the output should remain close to 3.3V even when the input voltage drops a bit below 3.3V. In this simulation, I allow Vin to drop as low as 2.9V to simulate worst case 12V vehicle cold cranking.) I also simulated it with a 300mA load, and the ESL spikes are even more massive than the above blue blob.
Below is how the output looks after I delete Series Inductance from C7 (the primary 22uF output capacitor) and from C4 (the INTVcc) capacitor. (For some reason LTSpice refuses to simulate when I only delete the Series Inductance of C7. I am forced to also delete the Series Inductance of C4 to get it to simulate, which baffles me. LTSpice bug? But the example is nevertheless sound, clearly showing that the lack of capacitor Series Inductances prevents occurrence of abnormally large ESL spikes.)
I know the ESL spikes have nothing to do with Anti-resonance pertaining to the output capacitors because I simulated that in a separate file and found the curve to be perfectly fine...
Here's the sim file for the above graph:
And to prove it's not Anti-resonance, here is the same test (no Series Inductance on C7 or C4), but this time without the ferrite bead and capacitor EMI filter on the output (still no major ESL spikes, although they are 107mVp-p, which is too large for my preference; but a ferrite bead EMI filter cleans that up quite nicely, as shown in the first output graph).
The problem has nothing to do with R7, the 100kΩ Mode resistor, since the problem results even with SSFM disabled. The two large input capacitors (330uF each) also have nothing to do with the problem, since the ESL spikes remain even without those two caps. DC Bias on the output capacitors it not the issue either. I even tried simulating PCB trace resistance by adding 2mΩ of resistance between output capacitors, but that had no effect on the ESL spikes.
While no simulation software is perfect, and while an actual circuit on PCB will determine if a problem exists, I did expect more of LTSpice this go around, now that it's been 4 years+ since my last simulation of a very similar circuit (same switcher IC, just with a different output voltage).
I would appreciate hearing your thoughts on whether this ESL spike issue remains a bug in LTSpice, or if there is something in my circuit that I am overlooking which is triggering the large 1.5Vp-p spikes when Series Inductance is used on all of the output capacitors.
P.S. BUG REPORT: There is a crashing bug in LT Spice XVII 17.0.42 for MacOS. To repeat the bug, open my *.asc file (linked earlier in this post), then right-click on the Load (I1), click the "Additional PWL points" button, select the bottommost Time/Value entry, click Delete, click OK, click OK, and then the app will crash. It happens every single time you try it.
7/7/2022: Added "P.S." Bug Report.
[edited by: KIRAMEK at 7:37 AM (GMT -4) on 7 Jul 2022]