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AD8561 LTSPICE simulation: latch problem

Good morning,

 

I would like to perform some SPICE simulations of the AD8561 comparator on LTSPICE software. However, I encounter some problems by using the .cir file from Analog Device website, and more particularly in the case of long time transient simulation (above 10µs).

 

The schematic of the test circuit I used for such purpose is sketched in Figure 1 with the corresponding results shown in Figure 2. In this setup, a constant voltage (noted Vcm) is set at the inverting input of the comparator. Meanwhile, a Heaviside signal (noted Vin) is applied to the non-inverting input of the comparator that is below and above Vcm respectively before and after t=5µs. Since the voltage applied to the latch is set by the voltage source V5 at 3V (i.e. latch set at its state “1”), the output should not vary after t=5µs and should consequently stay at its low state, that is not the case after around 9µs (see Figure 2).

 

Figure 1: Schematic of the testcircuit used for transcient simulation

 

Figure 2: Results of the simulation. The red signal (called V(ninv-in)) corresponds to the voltage applied to the non-inverting input of the comparator; the blue signal (called V(inv-in)) corresponds to the voltage applied to the inverting input of the comparator; and the green signal (called V(q)) corresponds to the output signal coming from the output Q of the comparator.

 

 

One possible reason of this problem could come from the latch section netlist (sketched in Figure 3). From this netlist, nodes 4 and 6 correspond to the inputs of the latch while node 12 is the output. As depicted in the SPICE netlist (Figure 3) and its corresponding schematic (Figure 4), the Latch contains different elements, more particularly a capacitor noted C3 of 10pF and a voltage controlled switch (noted S1 in the netlist) that goes from 500Ω to 1MΩ when the voltage applied to the latch is respectively below 1.4V and above 2.1V. Another particular element is the voltage controlled voltage source noted E2 with a gain of 1 that cancels the current entering in the resistor R3 of 500Ω.

The failure of the activated latch could be explained by the charge of the capacitor since the relaxation time τ is of around 10µs (that corresponds to the resistance of the switch on its off state and the capacitor C3).

 

 

Figure 3: SPICE netlist of the Latch Section (taken from the .cir file)

 

 

Figure 4: Latch section schematic corresponding to the SPICE netlist

 

 

I wanted to ask you if you could help me to understand why the latch does not work properly at long time, and if it is due to a possible mistake either on the netlist or on my test circuit.

 

Best regards,

 

Julien