LTC3623 - Simulation for negative output

Hi Ody, 

Can you share us your application circuit? thanks.

Regards,

Paul Daria

Sure! Here is the .asc file. Thanks for your help

fsm_psu.asc

Hi  Ody,

Thank you. I will forward your concern to its respective model owner and will get back to you once I get an update.

Unfortunately, I can only answer LTspice related concern eg. simulation issues, not model related issues.

Once they verify that the model itself contains bugs, we will have to fix it and update the model.

Thanks.

Regards,

PaulDaria

Thanks Paul!

Then do you think that it can be a problem in the model? Didn't you found any issue in regards to simulation/configuration?

Please keep me updated regarding this, as we will receive the development kit this week and I would like to try the same circuit of the schematic.

Best regards

Hi Ody,

I receive a confirmation that the issue is model related. it may take some time to resolve. I will let you know once its fixed and updated.

Thank you your feedback.

Regards,

PaulDaria

Thanks for the confirmation! Will wait for your updates.

Hi Ody,

Update is on its way. In about a day or two, please perform a sync release. You can find it under Tools>Sync Release.

Thank you for you  patience.

Regards,

Paul Daria

Thanks Paul, it seems to be working now. Can you please help me check the following?

1) In the same circuit, if I try to use an 80k feedback resistor (for setting the output voltage to -4 V), the output voltage can't go below -2.38 V and there is a high ripple current on the inductor (6 A peak to peak).

2) I need to set up the output voltage with an external source with an added offset of 0.3 V. In the positive configuration it is easy as I can put the required voltage directly into the ISET pin, but for the negative configuration I can't figure it out. What I did is the following:

Instead of connecting VOUT directly to GND, I'm putting the required voltage here. The 0.3 V offset is created by the 6 k resistor on ISET pin.

This configuration works but it has the same limitation of the point 1 (can't go below -2.38V) and it's creating a high inrush peak on the inductor:

Can you please confirm if this configuration can be used? Is there any way to configure the output voltage by using a positive supply instead of negative? As I don't want to add a secondary negative supply on the circuit.

Thanks again for your help!

Hi Ody,

This kind of question must be posted under Power by Linear Forum as that forum is being maintained by people more equipped with application related concern. This forum is for LTspice and/or simulations issue related questions only.

However since you already raise it here, I might as well provide you a solution.

Please read the datasheet carefully. This IC has several loops working together to generate/limit/control the output voltage.

you mentioned that the voltage clamps to -2.38V. this is because, the IMON pin is connected to GND.

Since you are operating at negative output, the PGND pin is connected to the negative output which is also the reference of all internal circuitry except those mentioned referenced to GSNS pin. with this scenario, when the output is equal to -2.35V, IMON sees it at +2.35V. thus limiting further reduction of voltage.

You can disable this feature by connecting it to the PGND instead. As much as the simulation is concern since this is the reference.

However, I am not sure if the actual part will work that way.

Please be careful on you testing. Happy simulation.

Thanks so much for your help!

Thanks so much for your help!