Ask a question about RC filter design at SAR ADC input terminal.

jerrytang - yes, I spent quite a bit of time trying to make sense of the equations in that paper as well!

The equation above is a variation on a capacitor discharge equation, as illustrated in https://www.analog.com/en/analog-dialogue/articles/front-end-amp-and-rc-filter-design.html

When thinking about ADC driving and looking at having your ADC inputs settled prior to the next sample, one of the factors at play is the size of the capacitance (a combination of capacitance that's internal to the ADC and capacitance in the external interface to the ADC) you want to be sure that the charge that is caused by any "kick" if fully settled to 1/2 lsb.  So the 1/2 lsb is the voltage we want to settle to during the acquisition time.

The Vstep is the voltage we're estimating was dumped on the capacitors when the kick event occurred - that's the voltage we're starting with at the beginning of acquisition that we want to be settled to 1/2 lsb by the end of acquisition.

And the ln() part is just the inverse of the e part of the capacitor discharge equations - we've just rearranged the equation so that we can find the t/RC portion of the equation, given the initial voltage and the desired settled voltage.

I've attempted to boil it all down in a video series - parts 1 and 2 would be relevant to your question.

https://www.analog.com/en/education/education-library/videos/video-series/input-driver-design-precision-sar-adcs-video-series.html

-Anne