LTSpice converter model problem

Hello,

I wanted to simulate our drivers board with multiple converters and transistors and have a problem with the converter TPS5436 and its spice model.

This model should work with pspice but won't work with LTSpice.

Any model experts here who know the problem?

Attached: Draft schematic and model.

Draft1.asc 

TPS54360_TRANS.txt
*$
* TPS54360
*****************************************************************************
* (C) Copyright 2014 Texas Instruments Incorporated. All rights reserved.                                            
*****************************************************************************
** This model is designed as an aid for customers of Texas Instruments.
** TI and its licensors and suppliers make no warranties, either expressed
** or implied, with respect to this model, including the warranties of 
** merchantability or fitness for a particular purpose.  The model is
** provided solely on an "as is" basis.  The entire risk as to its quality
** and performance is with the customer
*****************************************************************************
*
* This model is subject to change without notice. Texas Instruments
* Incorporated is not responsible for updating this model.
*
*****************************************************************************
*
** Released by: WEBENCH Design Center, Texas Instruments Inc.
* Part: TPS54360
* Date: 02SEP2014
* Model Type: TRANSIENT
* Simulator: PSPICE
* Simulator Version: 16.2.0.p001
* EVM Order Number: TPS54360EVM-182
* EVM Users Guide: SLVU769B�September 2012�Revised September 2012
* Datasheet: SLVSBB4E�AUGUST 2012�REVISED MARCH 2014
*
* Model Version: Final 1.10
*
*****************************************************************************
*
* Updates:
*
* Final 1.10
* Bug Fix: Added Hysteresis to OVP.
*
* Final 1.00
* Release to Web.
*
****************************************************************************
.SUBCKT TPS54360_TRANS BOOT COMP EN GND SW RT_CLK VIN FB ThermalPAD PARAMS: STEADY_STATE=0
R_thermal1 ThermalPAD 0 1m
R_thermal2 ThermalPAD 0 1m
V_V47         SET0 0 0Vdc
V_U6_V1         U6_N16588693 0 0.86
X_U6_U134         U6_N16564386 SDWN U6_N16543632 OR2_BASIC_GEN PARAMS: VDD=1
+  VSS=0 VTHRESH=500E-3
C_U6_C146         0 U6_N16489275  5p
X_U6_U603         PWM_CLK N16528816 SYSCLK SET1 U6_PWM SET1
+  DFFSBRB_RHPBASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
E_U6_ABM148         U6_N16489469 0 VALUE { {V(U6_VRAMPIN)*1u}    }
E_U6_ABM163         U6_N16502082 0 VALUE { LIMIT(((V(U6_N16488977) -
+  V(U6_VRAMP)) * 5)
+ -14.4u,-1.22u,61.2u)   }
X_U6_S26    U6_N16543632 0 U6_VRAMPIN 0 GmIphase_U6_S26
E_U6_ABM152         U6_ISWF 0 VALUE { {IF(V(U6_N16489275) > 0.5,
+ V(ISW),-0.1)}   }
R_U6_R255         U6_N16489395 U6_N16489275  14.4k
V_U6_V2         U6_N165858563 0 0.024
C_U6_C134         0 U6_VRAMPIN  1n
X_U6_U602         U6_N16575036 BOOT_UVLO U6_OVTP U6_PWM AND3_BASIC_GEN PARAMS:
+  VDD=1 VSS=0 VTHRESH=500E-3
E_U6_ABM165         U6_N16531938 0 VALUE { (V(U6_N16502082) * 91.4k)    }
D_U6_D58         U6_N16489275 U6_N16489395 D_D1
R_U6_R256         U6_N16531938 U6_ICTRL  1
E_U6_ABM164         U6_N16488977 0 VALUE { {((V(COMP) /123k)  - 4u)*3}    }
R_U6_R239         U6_N16489469 U6_VRAMP  1
G_U6_ABMI4         U6_VRAMPIN 0 VALUE { {V(IF2IA) * -1}    }
C_U6_C147         0 U6_ICTRL  1n
C_U6_C135         0 U6_VRAMP  1n
E_U6_ABM151         U6_N16489395 0 VALUE { {IF(V(PWM_FINAL) > 0.5, 1,0)}    }
X_U6_U599         SYSCLK U6_N16489527 INV_DELAY_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=0.5 DELAY=15n
X_U6_U600         U6_ICTRL U6_ISWF U6_N16575036 COMP_BASIC_GEN PARAMS: VDD=1
+  VSS=0 VTHRESH=0.5
X_U6_U598         SYSCLK U6_N16489527 U6_N16564386 AND2_BASIC_GEN PARAMS: VDD=1
+  VSS=0 VTHRESH=500E-3
X_U6_U604         U6_N16588693 VSENSEINT U6_N165858563 U6_OVTP
+  COMPHYS2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5 T=10
R_R1         GND 0  1m
V_V46         SET1 0 1
R_U3_R276         0 U3_N16489962  10G
R_U3_R282         U3_N16638112 VSENSEINT  1
R_U3_R277         U3_N16489962 RT_CLK  1
R_U3_R283         U3_N16667294 U3_N16667366  122.655
R_U3_R7         U3_N166379101 U3_N16638088  1
G_U3_G1         U3_N16490102 U3_RAMP U3_N16650384 0 1
C_U3_C79         U3_RAMP 0  1n
X_U3_H1    U3_N16489962 U3_N16523619 I_RT 0 Oscillator_U3_H1
E_U3_ABM164         U3_N16638112 0 VALUE { V(FB)    }
C_U3_C160         U3_N16667366 0  1n
X_U3_U6         U3_N16637796 VSENSEINT U3_OUT2 COMP_BASIC_GEN PARAMS: VDD=1
+  VSS=0 VTHRESH=0.5
E_U3_ABM1         FSW 0 VALUE { {(101756*1e-6)/((-1e-3/I(V_U3_V44))**1.008)}
+  }
V_U3_V46         U3_N16505459 0 1
X_U3_U131         U3_RAMP U3_N16505459 U3_SYSCLK1 COMP_BASIC_GEN PARAMS: VDD=1
+  VSS=0 VTHRESH=0.5
X_U3_U7         U3_N16638088 VSENSEINT U3_OUT3 COMP_BASIC_GEN PARAMS: VDD=1
+  VSS=0 VTHRESH=0.5
X_U3_U138         U3_SYSCLK1 U3_N16667366 SYSCLK OR2_BASIC_GEN PARAMS: VDD=1
+  VSS=0 VTHRESH=500E-3
C_U3_C161         0 IF2IA  1n
D_U3_D11         U3_RAMP U3_N16490102 D_D1
X_U3_U135         U3_SYSCLK1 U3_N16517387 BUF_DELAY_BASIC_GEN PARAMS: VDD=1
+  VSS=0 VTHRESH=0.5 DELAY=30n
R_U3_R278         I_RT 0  0.5
E_U3_ABM166         U3_N16676060 0 VALUE { IF(V(U3_OUT3) < 0.5, 660*V(I_RT),
+ IF(V(U3_OUT2) < 0.5, 330*V(I_RT),
+ IF(V(U3_OUT1) < 0.5, 165*V(I_RT), 82.5*V(I_RT))))  }
C_U3_C8         0 U3_N16668029  1n
D_U3_D12         U3_N16667294 U3_N16667366 D_D1
X_U3_U134         SDWN U3_N16517387 U3_N16517226 OR2_BASIC_GEN PARAMS: VDD=1
+  VSS=0 VTHRESH=500E-3
E_U3_ABM165         U3_N16650384 0 VALUE {
+  IF(V(U3_OUT3)<0.5,(101756*1e-6)/((-1e-3/I(V_U3_V44))**1.008),
+ IF(V(U3_OUT2)<0.5,(((101756*1e-6)/((-1e-3/I(V_U3_V44))**1.008))/2),
+
+  IF(V(U3_OUT1)<0.5,(((101756*1e-6)/((-1e-3/I(V_U3_V44))**1.008))/4),(((101756*1e-6)/((-1e-3/I(V_U3_V44))**1.008))/8))))
+   }
R_U3_R280         U3_N16676060 IF2IA  1
C_U3_C159         0 VSENSEINT  1n
E_U3_ABM7         U3_N166679551 0 VALUE { ((V(U3_OUT1)*25m) + 0.175)    }
C_U3_C7         0 U3_N16638088  1n
R_U3_R8         U3_N166679551 U3_N16668029  1
X_U3_S26    U3_N16517226 0 U3_RAMP 0 Oscillator_U3_S26
R_U3_R5         U3_N166378601 U3_N16637796  1
X_U3_U136         U3_SYSCLK1 U3_N16667326 U3_N16667294 AND2_BASIC_GEN PARAMS:
+  VDD=1 VSS=0 VTHRESH=500E-3
X_U3_U8         U3_N16668029 VSENSEINT U3_OUT1 COMP_BASIC_GEN PARAMS: VDD=1
+  VSS=0 VTHRESH=0.5
C_U3_C5         0 U3_N16637796  1n
V_U3_V44         U3_N16523619 0 1
E_U3_ABM4         U3_N166378601 0 VALUE { ((V(U3_OUT2)*50m) + 0.35)    }
V_U3_V45         U3_N16490102 0 5
X_U3_U137         U3_SYSCLK1 U3_N16667326 INV_DELAY_BASIC_GEN PARAMS: VDD=1
+  VSS=0 VTHRESH=0.5 DELAY=15n
E_U3_ABM6         U3_N166379101 0 VALUE { ((V(U3_OUT3)*75m) + 0.525)    }
X_U8_U606         SDWN U8_SDWN_N INV_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
X_U8_U613         SDWN U8_N7365280 INV_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
R_U8_R3         U8_N73698801 U8_N7345383  1
R_U8_R244         U8_N7274256 BOOT_UVLO  1
X_U8_U608         U8_HDRVIN U8_N7342498 U8_N7274022 AND2_BASIC_GEN PARAMS:
+  VDD=1 VSS=0 VTHRESH=500E-3
X_U8_U602         U8_OUT U8_BOOT_ON INV_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
X_U8_U607         U8_LDRV ENAB U8_BOOT_ON U8_SDWN_N U8_BOOT_SW_ON
+  AND4_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U8_U612         U8_N7274198 U8_N7343256 BUF_DELAY_BASIC_GEN PARAMS: VDD=1
+  VSS=0 VTHRESH=0.5 DELAY=10n
X_U8_U609         U8_N7343256 U8_N7274198 U8_N7274032 AND2_BASIC_GEN PARAMS:
+  VDD=1 VSS=0 VTHRESH=500E-3
C_U8_C140         0 BOOT_UVLO  1n
X_U8_H1    VIN U8_N7273984 ISW 0 Driver_U8_H1
E_U8_ABM2         U8_N73698801 0 VALUE { ((V(U8_OUT) *-500m)+ 6)    }
X_U8_S34    U8_BOOT_SW_ON 0 BOOT VIN Driver_U8_S34
C_U8_C3         0 U8_N7345383  1n
X_U8_U610         U8_HDRVIN U8_N7274198 INV_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
X_U8_U604         U8_N7365280 PWM_FINAL U8_HDRVIN AND2_BASIC_GEN PARAMS: VDD=1
+  VSS=0 VTHRESH=500E-3
E_U8_ABM169         U8_N7347010 0 VALUE { V(BOOT) - V(SW)    }
X_U8_U611         U8_HDRVIN U8_N7342498 BUF_DELAY_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=0.5 DELAY=10n
X_U8_S3    U8_N7274032 0 HDRV SW Driver_U8_S3
X_U8_U605         U8_HDRVIN U8_LDRV INV_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
E_U8_ABM167         U8_N7274256 0 VALUE { {IF((V(BOOT) - V(SW)) < 2.1,0,1)}
+  }
X_U8_S2    U8_N7274022 0 BOOT HDRV Driver_U8_S2
D_U8_D13         SW U8_N7273984 D_D1
X_U8_S30    HDRV SW U8_N7273984 SW Driver_U8_S30
R_U8_R245         0 BOOT  10MEG
X_U8_U5         U8_N7347010 U8_N7345383 U8_OUT COMP_BASIC_GEN PARAMS: VDD=1
+  VSS=0 VTHRESH=0.5
C_U5_C162         0 U5_N16512904  1n
C_U5_C9         0 OCB  1n
G_U5_ABM2I1         0 COMP VALUE { {LIMIT((V(VREF_GM) -
+  V(VSENSEINT))*V(U5_VGM), -30u,30u)}    }
D_U5_D10         COMP U5_N16513008 D_D1
E_U5_ABM177         U5_N16513064 0 VALUE { IF(V(U5_N16512904) < 77u, 77u,
+  IF(V(U5_N16512904) > 350u, 350u,V(U5_N16512904)))    }
X_U5_U603         SDWN U5_N16513124 INV_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
R_U5_R4         0 COMP  28.5714Meg
C_U5_C5         0 COMP  7.42f
R_U5_R286         U5_N16512948 U5_N16512904  1
E_U5_ABM8         U5_N16513186 0 VALUE { {IF(V(COMP) > 1.9,1,0)}    }
D_U5_U597         U5_N16513014 COMP D_D
V_U5_V6         U5_N16513008 0 2
C_U5_C166         0 U5_VGM  1n
R_U5_R290         U5_N16513064 U5_VGM  1
V_U5_V5         U5_N16513014 0 0.6
X_U5_U614         U5_N16513186 U5_N16513124 U5_N16513160 AND2_BASIC_GEN PARAMS:
+  VDD=1 VSS=0 VTHRESH=500E-3
R_U5_R11         U5_N16513160 OCB  1
E_U5_ABM171         U5_N16512948 0 VALUE { {IF(V(SS_TR) < 0.7, 70u, 70u + (240u
+  *((V(SS_TR) -700m)/299m)))}    }
X_U11_U604         ENAB U11_N16496294 INV_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
E_U11_ABM173         SS_DISCH 0 VALUE { {IF(V(SS_TR)  < 54m,0,
+ IF(V(U11_N6045136) > 0.5,1,0))}   }
X_U11_U601         U11_N16496294 U11_UVLO SDWN OR2_BASIC_GEN PARAMS: VDD=1
+  VSS=0 VTHRESH=500E-3
X_U11_U603         SDWN U11_N6045130 INV_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
V_U11_V64         U11_N6045018 0 4.3
R_U11_R287         0 U11_N6045136  1k
X_U11_U602         U11_N6045018 VIN U11_UVLO COMP_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=0.5
C_U11_C163         U11_N6045130 U11_N6045136  140.5p
C_U1_C1         0 ENAB  1n
D_U1_D9         EN VIN D_D1
E_U1_ABM173         U1_N7335522 0 VALUE { {IF(V(VIN) > 2.5,5,0)}    }
R_U1_R1         U1_N7335540 ENAB  1
R_U1_R256         EN U1_N7335522  100MEG
D_U1_D8         EN U1_N7335522 D_D1
E_U1_ABM1         U1_N7335540 0 VALUE { {IF(V(EN) < 1.2,0,1)}    }
G_U1_ABMII1         VIN EN VALUE { {1.2u+ 3.4u*V(ENAB)}    }
C_U7_C177         0 U7_INDELAYED2  10p
C_U7_C171         0 U7_N16490100  1n
R_U7_R273         U7_N16489586 U7_N16490100  1
X_U7_U6         U7_OR2OUT1 U7_OR2OUT2 U7_N16490100 PWM_FINAL MUX2_BASIC_GEN
+  PARAMS: VDD=1 VSS=0 VTHRESH=0.5
D_U7_U620         U7_N16489522 U7_INDELAYED1 D_D
X_U7_U826         PWM_CLK U7_N16509390 INV_DELAY_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=0.5 DELAY=15n
X_U7_U825         U7_N16509288 U7_INDELAYED2 PWM_CLK U7_OR2OUT2 OR3_BASIC_GEN
+  PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
E_U7_ABM13         U7_N16489586 0 VALUE { IF(V(COMP) <0.65 ,1,0)    }
R_U7_R276         U7_N16509288 U7_INDELAYED2  18k
X_U7_U823         U7_N16497188 PWM_CLK U7_N16489522 AND2_BASIC_GEN PARAMS:
+  VDD=1 VSS=0 VTHRESH=500E-3
X_U7_U827         U7_N16509390 PWM_CLK U7_N16509288 AND2_BASIC_GEN PARAMS:
+  VDD=1 VSS=0 VTHRESH=500E-3
C_U7_C172         0 U7_INDELAYED1  10p
R_U7_R272         U7_N16489522 U7_INDELAYED1  13.68k
D_U7_U623         U7_N16509288 U7_INDELAYED2 D_D
X_U7_U822         PWM_CLK U7_N16497188 INV_DELAY_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=0.5 DELAY=15n
X_U7_U824         U7_N16489522 U7_INDELAYED1 PWM_CLK U7_OR2OUT1 OR3_BASIC_GEN
+  PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
E_U4_ABM178         U4_N7398284 0 VALUE { IF(V(U4_N7404432) < 0.8,
+  V(U4_N7404432),0.8)    }
E_U4_ABM180         U4_N7398466 0 VALUE { IF(V(OCB) > 0.5,1,0)    }
V_U4_V70         U4_N7397990 0 1.7
D_U4_D62         SS_TR U4_N7397990 D_D1
G_U4_ABMII1         U4_N7397990 SS_TR VALUE { {IF(V(U4_N16518371) >
+  0.5,v(FSW)*0.7/1024,0)}    }
R_U4_R13         U4_N7404426 U4_N7404432  1
X_U4_U1         SDWN U4_N16518371 INV_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
D_U4_D63         0 SS_TR D_D1
X_U4_S68    U4_N7398492 0 SS_TR 0 SoftStart_U4_S68
E_U4_ABM179         VREF_GM 0 VALUE { IF({STEADY_STATE} < 0.5,
+  V(U4_N7398290),0.8)    }
G_U4_ABMI5         SS_TR 0 VALUE { {IF(V(SS_DISCH) > 2.5, 1.25e-3,0)}    }
R_U4_R14         U4_N7398284 U4_N7398290  1
C_U4_C8         0 SS_TR  1n
R_U4_R15         U4_N7398466 U4_N7398492  1
E_U4_ABM174         U4_N7404426 0 VALUE { IF(V(SS_TR) < 500m, V(SS_TR) - 34.4m,
+
+ IF(V(SS_TR) > 1500m, 0.8,
+ V(SS_TR) - ((0.6633*V(SS_TR)*V(SS_TR)) -(0.6493*V(SS_TR)) + 0.1802)))  }
C_U4_C12         0 U4_N7404432  1n
C_U4_C14         0 U4_N7398290  1n
C_U4_C15         0 U4_N7398492  100n 
C_U1_C99         EN 0 1p IC=0 
.IC         V(SS_TR )={STEADY_STATE*1.7}
.ENDS TPS54360_TRANS
*$
.subckt GmIphase_U6_S26 1 2 3 4
S_U6_S26         3 4 1 2 _U6_S26
RS_U6_S26         1 2 1G
.MODEL         _U6_S26 VSWITCH Roff=100e6 Ron=10m Voff=0.2 Von=0.8
.ends GmIphase_U6_S26
*$
.subckt Oscillator_U3_H1 1 2 3 4
H_U3_H1         3 4 VH_U3_H1 -1
VH_U3_H1         1 2 0V
.ends Oscillator_U3_H1
*$
.subckt Oscillator_U3_S26 1 2 3 4
S_U3_S26         3 4 1 2 _U3_S26
RS_U3_S26         1 2 1G
.MODEL         _U3_S26 VSWITCH Roff=100e6 Ron=1.0 Voff=0.2 Von=0.8
.ends Oscillator_U3_S26
*$
.subckt Driver_U8_H1 1 2 3 4
H_U8_H1         3 4 VH_U8_H1 1
VH_U8_H1         1 2 0V
.ends Driver_U8_H1
*$
.subckt Driver_U8_S34 1 2 3 4
S_U8_S34         3 4 1 2 _U8_S34
RS_U8_S34         1 2 1G
.MODEL         _U8_S34 VSWITCH Roff=1000e6 Ron=15 Voff=0.2 Von=0.8
.ends Driver_U8_S34
*$
.subckt Driver_U8_S3 1 2 3 4
S_U8_S3         3 4 1 2 _U8_S3
RS_U8_S3         1 2 1G
.MODEL         _U8_S3 VSWITCH Roff=1e6 Ron=1.0 Voff=0.2 Von=0.8
.ends Driver_U8_S3
*$
.subckt Driver_U8_S2 1 2 3 4
S_U8_S2         3 4 1 2 _U8_S2
RS_U8_S2         1 2 1G
.MODEL         _U8_S2 VSWITCH Roff=1e6 Ron=2 Voff=0.2 Von=0.8
.ends Driver_U8_S2
*$
.subckt Driver_U8_S30 1 2 3 4
S_U8_S30         3 4 1 2 _U8_S30
RS_U8_S30         1 2 1G
.MODEL         _U8_S30 VSWITCH Roff=10e6 Ron=92m Voff=1.0 Von=1.2
.ends Driver_U8_S30
*$
.subckt SoftStart_U4_S68 1 2 3 4
S_U4_S68         3 4 1 2 _U4_S68
RS_U4_S68         1 2 1G
.MODEL         _U4_S68 VSWITCH Roff=100e6 Ron=1047 Voff=0.2 Von=0.8
.ends SoftStart_U4_S68
*$
.model D_D1 d
+ is=1e-015
+ tt=1e-011
+ rs=0.05
+ n=0.1
*$
.model D_D d
+ is=1e-015
+ n=0.01
+ tt=1e-011
*$
.SUBCKT OR2_BASIC_GEN A B Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5
E_ABMGATE    YINT 0 VALUE {{IF(V(A) > {VTHRESH}  |
+ V(B) > {VTHRESH},{VDD},{VSS})}}
RINT YINT Y 1
CINT Y 0 1n
.ENDS OR2_BASIC_GEN
*$
.SUBCKT DFFSBRB_RHPBASIC_GEN Q QB CLK D RB SB PARAMS: VDD=1 VSS=0 VTHRESH=0.5
X1 CLK CLKdel INV_DELAY_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH} DELAY = 15n
X2 CLK CLKdel CLKint AND2_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH}
GQ 0 Qint VALUE = {IF(V(RB) < {VTHRESH},-1,IF(V(SB)< {VTHRESH},1, IF(V(CLKint)> {VTHRESH},
+ IF(V(D)> {VTHRESH},1,-1),0)))}
CQint Qint 0 1n
RQint Qint 0 1000MEG
D_D10 Qint MY5 D_D1
V1 MY5 0 1
D_D11 0 Qint D_D1
EQ Qqq 0 Qint 0 1
X3 Qqq Qqqd1 BUF_DELAY_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH} DELAY = 20n
RQq Qqqd1 Q 1
EQb Qbr 0 VALUE = {IF( V(Q) > {VTHRESH}, {VSS},{VDD})}
RQb Qbr Qb 1
Cdummy1 Q 0 1nF
Cdummy2 QB 0 1nF
.IC V(Qint) {VSS}
.MODEL D_D1 D( IS=1e-15 TT=10p Rs=0.05 N=.1 )
.ENDS DFFSBRB_RHPBASIC_GEN
*$
.SUBCKT COMP_BASIC_GEN INP INM Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5	
E_ABM Yint 0 VALUE {IF (V(INP) >
+ V(INM), {VDD},{VSS})}
R1 Yint Y 1
C1 Y 0 1n
.ENDS COMP_BASIC_GEN
*$
.SUBCKT COMPHYS2_BASIC_GEN INP INM HYS OUT PARAMS: VDD=1 VSS=0 VTHRESH=0.5	
+ T=10
EIN INP1 INM1 INP INM 1 
EHYS INM2 INM1 VALUE { IF( V(1) > {VTHRESH},-V(HYS)/2,V(HYS)/2) }
EOUT OUT 0 VALUE { IF( V(INP1)>V(INM2), {VDD} ,{VSS}) }
R1 OUT 1 1
C1 1 0 {T*1e-9}
RINP1 INP1 0 10K
RINM2 INM2 0 10K
.ENDS COMPHYS2_BASIC_GEN
*$
.SUBCKT AND3_BASIC_GEN A B C Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5
E_ABMGATE    YINT 0 VALUE {{IF(V(A) > {VTHRESH}  &
+ V(B) > {VTHRESH} &
+ V(C) > {VTHRESH},{VDD},{VSS})}}
RINT YINT Y 1
CINT Y 0 1n
.ENDS AND3_BASIC_GEN
*$
.SUBCKT INV_DELAY_BASIC_GEN A  Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 DELAY = 10n
E_ABMGATE1    YINT1 0 VALUE {{IF(V(A) > {VTHRESH} ,
+ {VDD},{VSS})}}
RINT YINT1 YINT2 1
CINT YINT2 0 {DELAY*1.3}
E_ABMGATE2    YINT3 0 VALUE {{IF(V(YINT2) > {VTHRESH} ,
+ {VSS},{VDD})}}
RINT2 YINT3 Y 1
CINT2 Y 0 1n
.ENDS INV_DELAY_BASIC_GEN
*$
.SUBCKT AND2_BASIC_GEN A B Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5
E_ABMGATE    YINT 0 VALUE {{IF(V(A) > {VTHRESH}  &
+ V(B) > {VTHRESH},{VDD},{VSS})}}
RINT YINT Y 1
CINT Y 0 1n
.ENDS AND2_BASIC_GEN
*$
.SUBCKT BUF_DELAY_BASIC_GEN A  Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 DELAY = 10n
E_ABMGATE1    YINT1 0 VALUE {{IF(V(A) > {VTHRESH} ,
+ {VDD},{VSS})}}
RINT YINT1 YINT2 1
CINT YINT2 0 {DELAY*1.3}
E_ABMGATE2    YINT3 0 VALUE {{IF(V(YINT2) > {VTHRESH} ,
+ {VDD},{VSS})}}
RINT2 YINT3 Y 1
CINT2 Y 0 1n
.ENDS BUF_DELAY_BASIC_GEN
*$
.SUBCKT INV_BASIC_GEN A  Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5
E_ABMGATE    YINT 0 VALUE {{IF(V(A) > {VTHRESH} ,
+ {VSS},{VDD})}}
RINT YINT Y 1
CINT Y 0 1n
.ENDS INV_BASIC_GEN
*$
.SUBCKT AND4_BASIC_GEN A B C D Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5
E_ABMGATE    YINT 0 VALUE {{IF(V(A) > {VTHRESH}  &
+ V(B) > {VTHRESH} &
+ V(C) > {VTHRESH} &
+ V(D) > {VTHRESH},{VDD},{VSS})}}
RINT YINT Y 1
CINT Y 0 1n
.ENDS AND4_BASIC_GEN
*$
.SUBCKT MUX2_BASIC_GEN A B S Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5
E_ABMGATE  YINT 0 VALUE {{IF(V(S) > {VTHRESH},
+ V(B),V(A))}}
RINT YINT Y 1
CINT Y 0 1n
.ENDS MUX2_BASIC_GEN
*$
.SUBCKT OR3_BASIC_GEN A B C Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5
E_ABMGATE    YINT 0 VALUE {{IF(V(A) > {VTHRESH}  |
+ V(B) > {VTHRESH} |
+ V(C) > {VTHRESH},{VDD},{VSS})}}
RINT YINT Y 1
CINT Y 0 1n
.ENDS OR3_BASIC_GEN
*$
.SUBCKT CESR IN OUT
+ PARAMs:  C=100u ESR=0.01 X=2 IC=0
C	IN 1  {C*X} IC={IC}
RESR	1 OUT {ESR/X}
.ENDS CESR
*$
.SUBCKT LDCR IN OUT
+ PARAMs:  L=1u DCR=0.01 IC=0
L	IN 1  {L} IC={IC}
RDCR	1 OUT {DCR}
.ENDS LDCR
*$

  • The errors:

    Questionable use of curly braces in "b§e_u6_abm148 u6_n16489469 0 v={v(u6_vrampin)*1u} "
    Error: undefined symbol in: "[v](u6_vrampin)*1u"
    Questionable use of curly braces in "b§e_u6_abm152 u6_iswf 0 v={if(v(u6_n16489275)>0.5,v(isw),-0.1)} "
    Error: undefined symbol in: "if([v](u6_n16489275)>0.5,v(isw),-0.1)"
    Questionable use of curly braces in "b§e_u6_abm164 u6_n16488977 0 v={((v(comp)/123k)-4u)*3} "
    Error: undefined symbol in: "(([v](comp)/123k)-4u)*3"
    Questionable use of curly braces in "b§g_u6_abmi4 u6_vrampin 0 i={v(if2ia)*-1} "
    Error: undefined symbol in: "[v](if2ia)*-1"
    Questionable use of curly braces in "b§e_u6_abm151 u6_n16489395 0 v={if(v(pwm_final)>0.5,1,0)} "
    Error: undefined symbol in: "if([v](pwm_final)>0.5,1,0)"
    Questionable use of curly braces in "b§e_u3_abm1 fsw 0 v={(101756*1e-6)/((-1e-3/i(v_u3_v44))**1.008)} "
    Error: undefined symbol in: "(101756*1e-6)/((-1e-3/[i](v_u3_v44))**1.008)"
    Questionable use of curly braces in "b§e_u8_abm167 u8_n7274256 0 v={if((v(boot)-v(sw))<2.1,0,1)} "
    Error: undefined symbol in: "if(([v](boot)-v(sw))<2.1,0,1)"
    Questionable use of curly braces in "b§g_u5_abm2i1 0 comp i={limit((v(vref_gm)-v(vsenseint))*v(u5_vgm),-30u,30u)} "
    Error: undefined symbol in: "limit(([v](vref_gm)-v(vsenseint))*v(u5_vgm),-30u,30u)"
    Questionable use of curly braces in "b§e_u5_abm8 u5_n16513186 0 v={if(v(comp)>1.9,1,0)} "
    Error: undefined symbol in: "if([v](comp)>1.9,1,0)"
    Questionable use of curly braces in "b§e_u5_abm171 u5_n16512948 0 v={if(v(ss_tr)<0.7,70u,70u+(240u*((v(ss_tr)-700m)/299m)))} "
    Error: undefined symbol in: "if([v](ss_tr)<0.7,70u,70u+(240u*((v(ss_tr)-700m)/299m)))"
    Questionable use of curly braces in "b§e_u11_abm173 ss_disch 0 v={if(v(ss_tr)<54m,0,if(v(u11_n6045136)>0.5,1,0))} "
    Error: undefined symbol in: "if([v](ss_tr)<54m,0,if(v(u11_n6045136)>0.5,1,0))"
    Questionable use of curly braces in "b§e_u1_abm173 u1_n7335522 0 v={if(v(vin)>2.5,5,0)} "
    Error: undefined symbol in: "if([v](vin)>2.5,5,0)"
    Questionable use of curly braces in "b§e_u1_abm1 u1_n7335540 0 v={if(v(en)<1.2,0,1)} "
    Error: undefined symbol in: "if([v](en)<1.2,0,1)"
    Questionable use of curly braces in "b§g_u1_abmii1 vin en i={1.2u+3.4u*v(enab)} "
    Error: undefined symbol in: "1.2u+3.4u*[v](enab)"
    Questionable use of curly braces in "b§g_u4_abmii1 u4_n7397990 ss_tr i={if(v(u4_n16518371)>0.5,v(fsw)*0.7/1024,0)} "
    Error: undefined symbol in: "if([v](u4_n16518371)>0.5,v(fsw)*0.7/1024,0)"
    Questionable use of curly braces in "b§g_u4_abmi5 ss_tr 0 i={if(v(ss_disch)>2.5,1.25e-3,0)} "
    Error: undefined symbol in: "if([v](ss_disch)>2.5,1.25e-3,0)"
    Questionable use of curly braces in "b§e_abmgate yint 0 v={if(v(a)>{{vthresh}}|v(b)>{{vthresh}},{{vdd}},{{vss}})}"
    Error: undefined symbol in: "if([v](a)>((vthresh))|v(b)>((vthresh)),((vdd)),((vss)))"
    Questionable use of curly braces in "b§e_abmgate yint 0 v={if(v(a)>{{vthresh}}&v(b)>{{vthresh}}&v(c)>{{vthresh}},{{vdd}},{{vss}})}"
    Error: undefined symbol in: "if([v](a)>((vthresh))&v(b)>((vthresh))&v(c)>((vthresh)),((vdd)),((vss)))"
    Questionable use of curly braces in "b§e_abmgate1 yint1 0 v={if(v(a)>{{vthresh}},{{vdd}},{{vss}})}"
    Error: undefined symbol in: "if([v](a)>((vthresh)),((vdd)),((vss)))"
    Questionable use of curly braces in "b§e_abmgate2 yint3 0 v={if(v(yint2)>{{vthresh}},{{vss}},{{vdd}})}"
    Error: undefined symbol in: "if([v](yint2)>((vthresh)),((vss)),((vdd)))"
    Questionable use of curly braces in "b§e_abmgate yint 0 v={if(v(a)>{{vthresh}}&v(b)>{{vthresh}},{{vdd}},{{vss}})}"
    Error: undefined symbol in: "if([v](a)>((vthresh))&v(b)>((vthresh)),((vdd)),((vss)))"
    Questionable use of curly braces in "b§e_abmgate yint 0 v={if(v(a)>{{vthresh}}|v(b)>{{vthresh}},{{vdd}},{{vss}})}"
    Error: undefined symbol in: "if([v](a)>((vthresh))|v(b)>((vthresh)),((vdd)),((vss)))"
    Questionable use of curly braces in "b§e_abmgate1 yint1 0 v={if(v(a)>{{vthresh}},{{vdd}},{{vss}})}"
    Error: undefined symbol in: "if([v](a)>((vthresh)),((vdd)),((vss)))"
    Questionable use of curly braces in "b§e_abmgate2 yint3 0 v={if(v(yint2)>{{vthresh}},{{vdd}},{{vss}})}"
    Error: undefined symbol in: "if([v](yint2)>((vthresh)),((vdd)),((vss)))"
    Questionable use of curly braces in "b§e_abmgate yint 0 v={if(v(a)>{{vthresh}}|v(b)>{{vthresh}},{{vdd}},{{vss}})}"
    Error: undefined symbol in: "if([v](a)>((vthresh))|v(b)>((vthresh)),((vdd)),((vss)))"
    Questionable use of curly braces in "b§e_abmgate yint 0 v={if(v(a)>{{vthresh}}&v(b)>{{vthresh}},{{vdd}},{{vss}})}"
    Error: undefined symbol in: "if([v](a)>((vthresh))&v(b)>((vthresh)),((vdd)),((vss)))"
    Questionable use of curly braces in "b§e_abmgate1 yint1 0 v={if(v(a)>{{vthresh}},{{vdd}},{{vss}})}"
    Error: undefined symbol in: "if([v](a)>((vthresh)),((vdd)),((vss)))"
    Questionable use of curly braces in "b§e_abmgate2 yint3 0 v={if(v(yint2)>{{vthresh}},{{vss}},{{vdd}})}"
    Error: undefined symbol in: "if([v](yint2)>((vthresh)),((vss)),((vdd)))"
    Questionable use of curly braces in "b§e_abmgate yint 0 v={if(v(a)>{{vthresh}},{{vss}},{{vdd}})}"
    Error: undefined symbol in: "if([v](a)>((vthresh)),((vss)),((vdd)))"
    Questionable use of curly braces in "b§e_abmgate yint 0 v={if(v(a)>{{vthresh}},{{vss}},{{vdd}})}"
    Error: undefined symbol in: "if([v](a)>((vthresh)),((vss)),((vdd)))"
    Questionable use of curly braces in "b§e_abmgate yint 0 v={if(v(a)>{{vthresh}}&v(b)>{{vthresh}},{{vdd}},{{vss}})}"
    Error: undefined symbol in: "if([v](a)>((vthresh))&v(b)>((vthresh)),((vdd)),((vss)))"
    Questionable use of curly braces in "b§e_abmgate yint 0 v={if(v(a)>{{vthresh}},{{vss}},{{vdd}})}"
    Error: undefined symbol in: "if([v](a)>((vthresh)),((vss)),((vdd)))"
    Questionable use of curly braces in "b§e_abmgate yint 0 v={if(v(a)>{{vthresh}}&v(b)>{{vthresh}}&v(c)>{{vthresh}}&v(d)>{{vthresh}},{{vdd}},{{vss}})}"
    Error: undefined symbol in: "if([v](a)>((vthresh))&v(b)>((vthresh))&v(c)>((vthresh))&v(d)>((vthresh)),((vdd)),((vss)))"
    Questionable use of curly braces in "b§e_abmgate1 yint1 0 v={if(v(a)>{{vthresh}},{{vdd}},{{vss}})}"
    Error: undefined symbol in: "if([v](a)>((vthresh)),((vdd)),((vss)))"
    Questionable use of curly braces in "b§e_abmgate2 yint3 0 v={if(v(yint2)>{{vthresh}},{{vdd}},{{vss}})}"
    Error: undefined symbol in: "if([v](yint2)>((vthresh)),((vdd)),((vss)))"
    Questionable use of curly braces in "b§e_abmgate yint 0 v={if(v(a)>{{vthresh}}&v(b)>{{vthresh}},{{vdd}},{{vss}})}"
    Error: undefined symbol in: "if([v](a)>((vthresh))&v(b)>((vthresh)),((vdd)),((vss)))"
    Questionable use of curly braces in "b§e_abmgate yint 0 v={if(v(a)>{{vthresh}},{{vss}},{{vdd}})}"
    Error: undefined symbol in: "if([v](a)>((vthresh)),((vss)),((vdd)))"
    Questionable use of curly braces in "b§e_abmgate yint 0 v={if(v(a)>{{vthresh}}&v(b)>{{vthresh}},{{vdd}},{{vss}})}"
    Error: undefined symbol in: "if([v](a)>((vthresh))&v(b)>((vthresh)),((vdd)),((vss)))"
    Questionable use of curly braces in "b§e_abmgate1 yint1 0 v={if(v(a)>{{vthresh}},{{vdd}},{{vss}})}"
    Error: undefined symbol in: "if([v](a)>((vthresh)),((vdd)),((vss)))"
    Questionable use of curly braces in "b§e_abmgate2 yint3 0 v={if(v(yint2)>{{vthresh}},{{vdd}},{{vss}})}"
    Error: undefined symbol in: "if([v](yint2)>((vthresh)),((vdd)),((vss)))"
    Questionable use of curly braces in "b§e_abmgate yint 0 v={if(v(a)>{{vthresh}},{{vss}},{{vdd}})}"
    Error: undefined symbol in: "if([v](a)>((vthresh)),((vss)),((vdd)))"
    Questionable use of curly braces in "b§e_abmgate yint 0 v={if(v(a)>{{vthresh}},{{vss}},{{vdd}})}"
    Error: undefined symbol in: "if([v](a)>((vthresh)),((vss)),((vdd)))"
    Questionable use of curly braces in "b§e_abmgate yint 0 v={if(v(a)>{{vthresh}}&v(b)>{{vthresh}},{{vdd}},{{vss}})}"
    Error: undefined symbol in: "if([v](a)>((vthresh))&v(b)>((vthresh)),((vdd)),((vss)))"
    Questionable use of curly braces in "b§e_abmgate yint 0 v={if(v(a)>{{vthresh}},{{vss}},{{vdd}})}"
    Error: undefined symbol in: "if([v](a)>((vthresh)),((vss)),((vdd)))"
    Questionable use of curly braces in "b§e_abmgate yint 0 v={if(v(a)>{{vthresh}}|v(b)>{{vthresh}},{{vdd}},{{vss}})}"
    Error: undefined symbol in: "if([v](a)>((vthresh))|v(b)>((vthresh)),((vdd)),((vss)))"
    Questionable use of curly braces in "b§e_abmgate yint 0 v={if(v(a)>{{vthresh}},{{vss}},{{vdd}})}"
    Error: undefined symbol in: "if([v](a)>((vthresh)),((vss)),((vdd)))"
    Questionable use of curly braces in "b§e_abmgate yint 0 v={if(v(s)>{{vthresh}},v(b),v(a))}"
    Error: undefined symbol in: "if([v](s)>((vthresh)),v(b),v(a))"
    Questionable use of curly braces in "b§e_abmgate1 yint1 0 v={if(v(a)>{{vthresh}},{{vdd}},{{vss}})}"
    Error: undefined symbol in: "if([v](a)>((vthresh)),((vdd)),((vss)))"
    Questionable use of curly braces in "b§e_abmgate2 yint3 0 v={if(v(yint2)>{{vthresh}},{{vss}},{{vdd}})}"
    Error: undefined symbol in: "if([v](yint2)>((vthresh)),((vss)),((vdd)))"
    Questionable use of curly braces in "b§e_abmgate yint 0 v={if(v(a)>{{vthresh}}|v(b)>{{vthresh}}|v(c)>{{vthresh}},{{vdd}},{{vss}})}"
    Error: undefined symbol in: "if([v](a)>((vthresh))|v(b)>((vthresh))|v(c)>((vthresh)),((vdd)),((vss)))"
    Questionable use of curly braces in "b§e_abmgate yint 0 v={if(v(a)>{{vthresh}}&v(b)>{{vthresh}},{{vdd}},{{vss}})}"
    Error: undefined symbol in: "if([v](a)>((vthresh))&v(b)>((vthresh)),((vdd)),((vss)))"
    Questionable use of curly braces in "b§e_abmgate yint 0 v={if(v(a)>{{vthresh}}&v(b)>{{vthresh}},{{vdd}},{{vss}})}"
    Error: undefined symbol in: "if([v](a)>((vthresh))&v(b)>((vthresh)),((vdd)),((vss)))"
    Questionable use of curly braces in "b§e_abmgate1 yint1 0 v={if(v(a)>{{vthresh}},{{vdd}},{{vss}})}"
    Error: undefined symbol in: "if([v](a)>((vthresh)),((vdd)),((vss)))"
    Questionable use of curly braces in "b§e_abmgate2 yint3 0 v={if(v(yint2)>{{vthresh}},{{vss}},{{vdd}})}"
    Error: undefined symbol in: "if([v](yint2)>((vthresh)),((vss)),((vdd)))"
    Questionable use of curly braces in "b§e_abmgate yint 0 v={if(v(a)>{{vthresh}}|v(b)>{{vthresh}}|v(c)>{{vthresh}},{{vdd}},{{vss}})}"
    Error: undefined symbol in: "if([v](a)>((vthresh))|v(b)>((vthresh))|v(c)>((vthresh)),((vdd)),((vss)))"
    Questionable use of curly braces in "b§e_abmgate yint 0 v={if(v(a)>{{vthresh}},{{vss}},{{vdd}})}"
    Error: undefined symbol in: "if([v](a)>((vthresh)),((vss)),((vdd)))"
    Questionable use of curly braces in "b§e_abmgate1 yint1 0 v={if(v(a)>{{vthresh}},{{vdd}},{{vss}})}"
    Error: undefined symbol in: "if([v](a)>((vthresh)),((vdd)),((vss)))"
    Questionable use of curly braces in "b§e_abmgate2 yint3 0 v={if(v(yint2)>{{vthresh}},{{vss}},{{vdd}})}"
    Error: undefined symbol in: "if([v](yint2)>((vthresh)),((vss)),((vdd)))"
    Questionable use of curly braces in "b§e_abmgate yint 0 v={if(v(a)>{{vthresh}}&v(b)>{{vthresh}},{{vdd}},{{vss}})}"
    Error: undefined symbol in: "if([v](a)>((vthresh))&v(b)>((vthresh)),((vdd)),((vss)))"
    Questionable use of curly braces in "b§e_abmgate1 yint1 0 v={if(v(a)>{{vthresh}},{{vdd}},{{vss}})}"
    Error: undefined symbol in: "if([v](a)>((vthresh)),((vdd)),((vss)))"
    Questionable use of curly braces in "b§e_abmgate2 yint3 0 v={if(v(yint2)>{{vthresh}},{{vdd}},{{vss}})}"
    Error: undefined symbol in: "if([v](yint2)>((vthresh)),((vdd)),((vss)))"

  • +1
    •  Analog Employees 
    on Oct 25, 2020 7:51 PM 1 month ago in reply to lopichler

    lopichler,

    If you have questions about the compatibility of this model outside of PSpice, you'll need to contact the vendor who supplied the model.  Sorry I'm not able to help.

    -Anne