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Using the alternative AD9528 clocking without ADF4360-7

Category: Hardware
Product Number: AD-FMCLIDAR1-EBZ

We've a custom design based on the EVM.

In the guides here:

It mentions:

The DAQ board allows for an alternative use of the AD9528 where both its PLL stages are used in addition to the output buffer. This option doesn’t use the separate PLL – ADF4360-7. The block diagram along with the higher power consumption are given in the next figure.

Our hardware engineers have chosen to implement this way of clocking. So now it's up to me to get this to actually work. This complicates the AD9528 settiings considerably, since the PLLs will no longer be in bypass.

Is there a devicetree available that contains the settings that are to be used here?

So far I figured out that:
adi,pll2-m1-frequency = <1000000000>;

lets the driver calculate most of the settings for PLL2. For PLL1 it's not clear to me what needs to be done. Just like the reference design, there's a 25MHz oscillator and a 122.88MHz VCXO