TOF PCB Requirements


I have a few general questions regarding the PCB level considerations that are to be followed for TOF board.My questions are as follows:

  • Should LD signals be length matched? If yes, what is the maximum allowable skew between  LD signals? Also, what is the maximum trace length, LD signals can have?
  • Is there any specific trace impedance to be maintained for the LD signals?
  • How critical is the sync between LD5 and other LD signals (LD1 to LD4)?


  • +1
    •  Analog Employees 
    on Sep 1, 2020 12:06 PM 2 months ago

    LD1 to LD4 must be length matched. The max allowable skew is 2-3 mils. There are no specific requirements on the trace length.

    There is no specific trace impedance to be maintained, but it's important to have controlled impedance for all the LD signals.

    LD5 does not need to be length matched to the other LD signals.

  • Thanks for the reply.

    Since 2-3 mils to is very low, do we have internal options in ADI Processor to compensate for the offset in timing between LD1 to LD4?

    My understanding on LD5 and LD(1 to 4) signals in that, LD5 is for readout from sensor and LD (1 to 4) is for illumination. So, if length matching is not done, there will be no sync between readout(LD5) and illumination(LD 1 to 4). Will this not cause errors in accuracy?

    In ADI-96 board, ADP3624ARHZ is used as MOSFET Gate Driver. In the datasheet of this part, there is data for typical and maximum raise,fall,on delay and off delay timings. Can you please let me know the minimum values of the above mentioned parameters. Please refer the below image.