I have a few general questions regarding the PCB level considerations that are to be followed for TOF board.My questions are as follows:
- Should LD signals be length matched? If yes, what is the maximum allowable skew between LD signals? Also, what is the maximum trace length, LD signals can have?
- Is there any specific trace impedance to be maintained for the LD signals?
- How critical is the sync between LD5 and other LD signals (LD1 to LD4)?