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FAQ: DDS Tutorial - The DAC Reconstruction Filter
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Direct Digital Synthesis (DDS) requires membership for participation - click to join
Documents
14-bit DDS to Output Triangle Waveformt at speeds >75MHz
32-bit Resolution or 64-bit Resolution Mode
64 bit Windows compatibility
Achieving optimal performance from the AD9914/AD9915
AD5930 evaluation software running on Windows 7
AD5930 Gotcha's
AD5933- Calculating Calibration Resistance Values
AD5933: DC Output Impedance
AD5933: Measurement of Capacitance and Resistance
AD5933_AN847 equation6 error
AD5934 measuring impedances at low frequencies
AD5934 questions - measuring inductive reactance
AD9152: Phase Noise Curves and Comparison with AD9912-DDS
AD9830:
AD9830: oscillator
AD9832: Driving from LVCMOS
AD9832: Seperated DGND and AGND
AD9833: Difference between AD9833 and AD9834
AD9833: Disconnecting the MCLK
AD9833: Sine generator
AD9834: MSB output jitter reduction
AD9834: Operation of DDS
AD9835: DC offset cancelation
AD9835: FSK transmitter
AD9838 Datasheet error: Absolute maximum ratings for AVDD to DVDD
AD9838 DDS power consumption
AD983x family and Sawtooth Waveform generation
AD9840: Operation at 20 MHz
AD9840A: clock rate
AD9845A AD9845A: Using the CCDIN with a DC level up to 4.8V
AD9850 questions
AD9850 searching for the "Dxocx.dll" AD9850_About Dxocx.dll file of AD9850EVB software
AD9850: Noise coupling on analog output
AD9850: output frequency
AD9851: Best value for Rset
AD9851: frequency senthesis
AD9851: RESET input
AD9852: Evaluation board output amplitude is always full scale?
AD9854 Clock Driver
AD9854: digitally controlled oscillator
AD9854: Sequence for writing new data to the programming registers
AD9854: Time between rising edge of UDCLK and the start of the waveform
AD9854ASQ: Pin connection
AD9854_FSK toggle rate
AD9856: Pin connection
AD9857: FUD signal
AD9857: Producing a sinc wave with DDS
AD9858: EVB VCO datasheet
AD9858: Output frequency change
Ad9858: Reading data back
AD9858_unused input pins connection
AD9858_unused power pins connection and saving power measures
AD9910 and AD9912: Residual Phase Noise Definition and Measurement
AD9910 Evaluation board driver for Win7
AD9910 frequency update rate
AD9910: EVB R43 resistor value
AD9910: output circuit clarification
AD9910: output filter design
AD9910: Programming through SPI-Interface
AD9910: REFCLK termination
AD9910: REFCLK termination 2
AD9910EVB_Filter Question
AD9910_Multichip SYNCHRONIZATION.
AD9910_output amplitude flatness over frequency
AD9910_phase noise
AD9910_phase truncation bits
AD9912: maximum PFD frequency
AD9912: multichip synchronization
AD9912: Sync multiple devices
AD9914 - connection to an uC
AD9914 pahse wheel and spur relationship and synchronisation query
AD9914/AD9915 Programmable Modulus Mode Tuning Resolution
AD9914/AD9915 REFCLK Multiplier
AD9914/AD9915 SFDR Specification
AD9914/AD9915 Super Nyquist Zones
AD9915 for best phase noise performance
AD9915/PCBZ user guide: where can I find it?
AD9945 addtion of Startup Register (PCN 11_0006). How to handle mixed stock of parts pre and post PCN
AD9951 - RefCLK using external Oscillator instead of Crystal
AD9951: Clock signal
ad9951: REFCLK input considerations
AD9951: REFCLK inputs
AD9952: Eval board
AD9952: Pin connection
AD9952: Pin connections
AD9952: Pin function of 47 and 48
AD9953: Crystal specification
AD9953: Design questions
AD9953: Generating a signal in the 50-90MHz range
AD9953: How to write RAM
Ad9953: Several issues
AD9954 phase/amplitude dithering
AD9954 power consumption on power down?
AD9954's output compliance voltage dependencies?
AD9954: DACP pin connected to AGND
AD9954: Effect of REF CLK
AD9954: RAM continuous recirculate mode, start phase information
AD9954: Spur at SYSCLK/4
AD9954: Synchronization of 16 AD9954
AD9954: What is the relationship between the power consumption and the frequency of the system clock?
AD9956 linear sweep (no dwell disabled) has a glitch when the FTW0 is changed to a lower value after a ramp-up
AD9956: Run-time error 13
AD9957: maximum signal bandwidth
AD9957AD9910_Matched Latency Enable Bit
AD9957_CCI overflow
AD9958: Timing of SCLK for a data read operation
AD9959 evaluation board clock
AD9959: ADIsimDDS_spectrum
AD9959: FSK modulation performance
Ad9959: Oscillator
Bit 2 in address 0x0200 in I/O register - HSTL driver
Can I use a DDS to produce modulation waveforms?
Can I use the AD9859 without using external components to create a square wave?
Can the AD9957 Evalboard and software generate CDMA modulation of the AD99957?
Can you send me the AD9856 filter coefficients?
DDS Features Chart
DDS for space or Radiation Hard Specifications
DDS_harmonic or image phase adjustment
DIRECT DIGITAL SYNTHESIS (DDS) SUPPORT COMMUNITY
Documentation error: AN-1108 application note, AD9832 analog output on reset is incorrect
Does your DDS evaluation software work on Windows XP/Vista/7/8 32-bit/64-bit?
Eval kit for AD9951, AD9952, AD9953 and AD9954
Execution error 13 Type incompatible
FAQ: Are any of your DDS products space qualified?
FAQ: Are there any specific recommendations regarding via fill material in the circuit board for the thermally enhanced package styles associated with some ADI DDSs?
FAQ: DDS Tutorial - Introduction to DDS
FAQ: DDS Tutorial - SINC Envelope Correction
FAQ: DDS Tutorial - The Accumulator
FAQ: DDS Tutorial - The Angle-to-Amplitude Converter
FAQ: DDS Tutorial - The DAC
FAQ: DDS Tutorial - The DAC Reconstruction Filter
FAQ: DDS Tutorial - The DDS in Action
FAQ: DDS Tutorial - User Guide
FAQ: Do you recommend a linear or switching power supply?
FAQ: How does the REF CLK performance affect the DDS output performance?
FAQ: How often should I send an I/O_UPDATE when I write to multiple registers?
FAQ: Is there a relationship between the sample rate and the maximum update rate?
FAQ: Is there information available on proper soldering and assembly techniques for thermally enhanced packages?
FAQ: Learning more about Direct Digital Synthesis Technology (DDS)
FAQ: What does the programmable modulus feature provide?
FAQ: Why isn't the SFDR of my DDS with 14 bit DAC better than the SFDR of one with a 10 bit DAC?
FAQ: Why would I choose to use DDS for synthesizing a signal rather than a PLL?
general usage of the AD9850
How can I perform amplitude modulation using the AD9835?
How do ADI's DDS engines compare to FPGA-based DDS engines?
How to manually select the device driver used by the Evaluation software?
In most of DDSs’ datasheet, analog ground (AGND) and digital ground (DGND) pins are separate, but in most of the DDS evaluation boards AGND and DGND pins are not separated. Why?
Is Data Valid Time (tDV) of 12nS for AD9959 correct? Or should it be 1.2nS instead?
Is it okay to use a frequency modulated (FM) source as my clock input to the system clock of the DDS?
Is it possible to start a negative sweep using the digital ramp generator of the DDS?
Is the AD9914's EPAD internally connected to AGND or DGND?
Problems with Evalboard for AD5930, EVAL-AD5930EBZ
RE AD5933 Capacitance Measurement
Running the AD9914 faster than 3.5GHz
Sine wave generator
The AD9959's SYNC_CLK has no signal. What should I check to fix this?
the introduction document of AD9954 evaluation
Trouble programming AD5932 Evaluation Board
Under what conditions is it OK to use the on-board PLL multiplier?
What are the basic things to be checked when using the DDS evaluation board via external control?
What is the difference between the AD9914 and AD9915?
What is the function of the SYNC_IO pin on the DDS parts?
What kind of problems might I expect from exceeding the maximum clock rate?
What number would I write to the Phase Adjust Register to get for example 10 degrees?
What’s the function of the SYNC_CLK pin on the DDS?
Where can I find in the datasheet on how the output of the DDS will drift?
Why does a DDS need a reconstruction filter?
Why does my narrowband spectral performance degrade when using larger values of multiplication on the internal reference clock multiplier (PLL)?
FAQ: DDS Tutorial - The DAC Reconstruction Filter
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23 Aug 2018 8:09 PM
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4 Jun 2018 5:10 PM
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