Q: Under what conditions is it OK to use the on-board PLL multiplier?
A: It can be enumerated by the following:
- When using a low frequency system clock source, because the PLL multiplier translates the low frequency input source to a more suitable high frequency system clock.
- For applications with a relatively relaxed phase noise (i.e., jitter) requirement, because the phase noise of the integrated VCO in the PLL multiplier cannot compete with a high quality RF source.
- For applications that do not demand very good close-in (low offset) phase noise performance, because the PLL amplifies noise within its closed loop bandwidth, which negatively impacts close-in phase noise.
This FAQ was generated from the following discussion: Under what conditions is it OK to use the on-board PLL multiplier?
