When you you reset the part, it should go to 0 Hz and the phase will be the
cosine of 0 degrees. This means that the output will be a DC current pumping
out 10 mA to the load.
The latency from RESET active to cosine 0 o/p is similar to a phase latency of
a min of 13 SYSCLK.
When you power up the AD9850, the input registers are full of unknown bogus
data. Even a reset does not clear the input registers. Now, if you transfer
that nasty data to be processed (by asserting a FQ_UD) and one or all of W32,
W33 or W34 are high, then that is bad...the part may power down, enter a
factory test mode, or go into a PLL mode that will multiply the input clock by
4X! The way to avoid this is as follows:
1. Reset the part after power-up, check the o/p is at cosine0 after a min of
2. Write to the part as per page 10 fig13, if you to have a problem to change
the freq, set up the first write to be all zeros, this will clear out the
bogus data from power up on the first FQ_UD assert.
With reference to your query below, by using the same master clk and a common
FQ_UD for both parts and taking into account the above data you should not have
an issue with generated two signals 0 and 90degrees out of phase.