toggle between the instruction cycle and the data transfer cycle?
I would not recommend it, the SDO and SDIO pins go to a high impedance state
when the CS is high. In the datasheet it says that If CS is driven high during
any communications cycle, that cycle is suspended until CS is reactivated low.
Chip select (CS ) can be tied low in systems that maintain control of SCLK.
Page 47 shows the timing diagrams for serial port reading and writing, CS
should be low during both the instruction and the data transfer cycle.