AD9910 had the phase difference. If so, whether we can configure some registers
in the AD9910 to remove the phase difference?
So appreciated you can give me some advices!
They're three basic requirements to synchronize multiple DDSs using the auto
1) Coincident REF CLK to all DDSs
2) Coincident SYNC_CLKs across all DDSs
3) Synchronous IO_UPDATE sent to all DDSs.
1) Coincident REF CLK to all DDSs...............Self explanatory. Note, if the
REF CLKs are misaligned across DDSs, the SYNC_CLK will also be misaligned by
the same amount. The SYNC_CLK is the System Clock divided by four. The internal
digital circuitry runs at the SYNC_CLK rate. Data enters the DDS core on a
SYNC_CLK rising edge. Therefore you must use the IO_UPDATE synchronously
(setup/hold) to the SYNC_CLK. The IO_UPDATE and SYNC_CLK transfers the new data
changes to the DDS core from the I/O buffers (data inactive).
2) Coincident SYNC_CLKs at all DDSs.....The synchronization circuitry on the
DDS manages this part only. It assumes the REF CLKs are aligned. If so, the
SYNC_CLK (at power up) are in one of four phase states (0, 90, 180, 270). The
goal is to get all DDS's SYNC_CLKs at 0 degrees. That's what the
synchronization circuit does (only) You still must sent a synchronous IO_UPDATE
to all DDSs. For more the synchronization circuit feature please refer to the
3) Synchronous IO_UPDATE sent to all DDSs that meets setup and hold times to
the SYNC_CLK....... To synchronize two evaluation boards, you "might" be able
to put the IO_UPDATE in manual mode and it work. At the top of the GUI is a
check box labeled "Auto I/O Update". If you uncheck the box you can sent a
Manual I/O Update to both boards. You'll have to tie both the I/O_UPDATE pins
together to make common. If this doesn't work, you'll probably need to run the
IO_UPDATE thru an external flip flop clocked by SYNC_CLK to both DDSs. The
evaluation boards have header connectors to gain access to the DDS pins.
In auto mode, if you lose synchronization via the power down feature, it should
automatically re-synchronize upon power-up.