The maximum input frequency range is 200MHz without SYSCLK PLL Doubler shown as
the figure 1.
But the maximum input rate of system clock PFD is only 100MHz, so I think the
actual input of SYSCLK should not exceed 100MHz. Is that correct? If so, there
should be something wrong with the datasheet.
The maximum PFD frequency should change to 200MHz. We will make a change at
next revision of the datasheet.