data in a Xilinx FPGA. As indicated in AD9152 DS, Figure 31 –
The questions and answers related are specified as below.
· Question - As I understand the clocking is performed by SMA100A
signal generator. What frequency has the generator on the different tracks ?
Measurements with PLL off were made with SMA100A output = 1.96608Ghz.
Measurements with PLL on were made with SMA100A output = 51MHz.
· Question – Is the generator used at 51MHz and then multiplied to 1966.08MHz?
Yes for all the PLL on measurements
· Question – There is PLL ON and OFF curves. How are they created using
SMA100A? When the PLL is OFF, do we change the frequency of SMA100A to
· This is not a question but a comment- 51MHz SMA100A Input Signal is indicated
with legend blue but the depicted phase noise is in black. May be that requires
a correction of the legend for future DS revision. Yes this correction should
· Question- Comparing the phase noise of AD9152 with the AD9912 DDS, Figure 23
for example gives as result that the AD9152 is 20 dB or so worse than AD9912.
Why is it so? Is it possible to reach the same level with AD9152 and a
reference with low phase noise? The customer expect to have a 1200 MHz
reference with phase noise 1 kHz/-122, 10 kHz/-137, 100 kHz/-146, 1 MHz/-156,
10 MHz/-163 dBc/Hz. The generated single frequency shall be around 350 MHz in a
relatively narrow band (+/- 20 MHz). What we’re seeing in the AD9152 chart is
the inherent phase noise performance limit of the DAC core. The AD9152 measured
phase noise is not coming from the clock power supply and it is not coming from
the clock source. The AD9912 DAC core just has better phase noise performance.