The limitation to AVDD +/-0.5V comes from the use of a transformer and the
If I use a resistor the ouput compliance voltage windows will became AVDD to
AVDD-0.5V ?so half of it?
The output voltage limitation is from the DAC itself. The DAC outputs should be
the proper load impedance in order to limit the output voltage swing so that it
is within the voltage compliance limits of the output stage. Both DAC outputs
(true and complementary) should be terminated with the same resistance for best
SFDR performance, and to limit harmonic distortion at higher output
frequencies. In most cases this should be 50 ohms. Remember the output voltage
compliance range is "AVdd +/- 0.5V".
To calculate the peak to peak voltage at the complementary DAC outputs, simply
multiply the full scale current by the equivalent output load. Note, the DAC
outputs are open drain and must be dc terminated for current flow. Whatever
output network is used (termination resistors + filter + transformer, etc) the
equivalent load must be used for the peak to peak voltage (Vpp) calculation.
Again, Vpp = full scale current * equivalent load. For instance, say there's
two 50 ohm output termination resistors at the DAC driving a differential
filter with a 100 ohms at the output of the filter. The equilvalent load at
each DAC output is 25 ohms.
Since the AD9954's DAC outputs are referenced to AVDD (current sinking DAC),
not ground (current sourcing DAC), the output common mode voltage for both
outputs is (AVDD - Vpp/2). Note, if the DAC outputs are terminated into a
transformer or inductors referenced to AVDD, the DAC output will swing about
AVDD. In that case, the common mode voltage is AVDD.