Q
In AD9951 datasheet, the description of reference clock signal is limited. It
is specified only the max applicable power. Can you confirm that using
sinusoidal signal is equivalent than squared (ECL?) signal? What is the impact
on DDS phase noise? Using differential input can lead a better phase noise than
single ended input?
A
The AD9951 reference input is normally driven with a sine wave.
It is AC coupled (with a capacitor) and if a single-ended drive is used the
other clock input is decoupled with another capacitor.
The drive level must not be over 1.8 V pk-pk (0.64 V r.m.s.) with a 1.8V
supply, but may be as low as 100 mV r.m.s.
However it is better to use as large a drive as possible to minimise phase
noise.
If you drive the reference input with a square wave it must have a duty cycle
of close to 50% and logic levels (for 1.8V supply) of logic 0<.4V and logic
1>1.25V.
If you use the PLL clock multiplier with logic inputs the duty cycle may be
slightly worse - between 35% and 65%.
Driving differentially is more recommended. Better common mode rejection is
achieved.