help us with that because the struggle costs lots of time.
1) Power sequencing
We have AVDD, DVDD = 1.8V and VDDIO = 3.3V, which supply has to be powered up
first? Simultaneous powerup is not possible, but the order may be controlled.
Is the AD9953 damaged if power sequence is wrong?
2) SPI comm with I/O Update pin
Right now we try to get AD9953 SPI I/O running but it worksn't right. We
managed to write config registers 1+2 ok once, but reading them back never
worked (always wrong data).
The states/timing seems to be ok on the logic channels.
SYNC_CLK is not used, it's a single device.
We pull down CSn and I/O Update, write the instruction byte, wait 1µs
(optional), write the correct number of data bytes, pull up I/O update (rising
edge for data latch) and pull up CSBn.
Is that ok?
Do we have to toggle I/O Update when reading data, too? If yes, when do we have
to toggle it?
For a short moment, we managed to also write the frequency register and got a
sine output. After writing the frequency register often after each other the
device stopped working. We have no idea why.
Right now, we don't even manage to write the config registers correct any more,
the "SDIO Input only" seems not to be activated and PLL Multiplier cannot be
set correctly. 3 Prototypes have been built, none talks correctly.
3) Is a Reset via the RESET pin also resetting the I/O system (meaning the same
as IOSYNC pin) ?
1. Power sequencing
There is no specific requirement on AD9953 for power sequencing. We have not
seen any parts experienced damage due to power sequencing. In my view, if your
system power up AD9953 on DVDD, AVDD, and DVDD-I/O within fractions of second,
it should not have any problems.
2.SPI comm with I/O Update pin
After AD9953 hardware reset, the SPI is default to “2 wire” SPI mode. There is
a mistake on Page 27 of datasheets in the “SDIO” description that said “… Bit 7
of Register Address 0x00 controls the configuration of this pin.” It should be
Bit 9 of Register Address 0x00. Please refer Page 14 and 17 for CFR1<9> (Bit 9
of Register 0x00) detailed description.
Based on the information you provided, you were using “3 wire” SPI mode,
therefore, after AD9953 resets, CFR1<9> should be set to 1 (high) in order to
configure to “3 wire” SPI.
You did not indicate how AD9953 SPI in your system was driven. Please pay
attention to the clock stall between “instruction cycle” and “data transfer
cycle”: if you were using a micro-controller and its standard serial port to
drive the SPI, it may clock continuously. So when you insert “1uS” between the
cycles, any clock line toggling may violate the clock stall requirement. If you
were using a standard I/O pin to toggle the clock line of the SPI, be sure you
have proper clock stall between the cycles.
AD9953 SPI writes the data on the SCLK rising edges. The data is driven out of
AD9953 on the SCLK falling edges. Please read Page 26 and Figure 24 and Figure
26 for the difference of two different clock stalls on SDO line. In Figure 24
clock stall low case, Do7 actually is ready when last clock falling edge in
Phase 1, or instruction cycle, occurred; in Figure 24 clock stall high case,
Do7 is ready when stalled high clock falling edge in Phase 2, or data transfer
cycle, occurred. Also make sure you bring CS signal high after eight (8)
falling edges complete during reading back.
I noticed that you said you pulled up I/O Update and pulled up CS, but you did
not indicate the timing when you pulled them up. The CS signal only controls
SPI I/O buffer, when data writing or reading is over, it should be pulled up.
The I/O Update signal controls data in the SPI I/O buffer transferring to
active registers, please see Figure 21 on Page 24. The timing should be CS pull
up first, then I/O Update pull up to give a rising edge to trigger data
transferring from I/O buffer to the active registers. Please pay attention to
I/O Update rising edge that is detected by SYNC_CLK, see Figure 22. For this
reason, I/O Update does not have to hold its level (because its level does not
matter, but only its rising edge does) once SYNC_CLK detects its rising edge
(on Page 24, notes 2 describes this). The I/O Update has 4nS setup time, and
its returning back to low (has to stay low for at least one SYNC_CLK cycle)
then pulling back to high will initiate another data transferring from I/O
buffer to the active registers.
As you can see from above, during the read back, I/O Update should not be
toggled, because read back only operates between external device and the SPI
3.Hardware Reset resets entire AD9953, which means it puts all registers in
their default. IOSYNC is a sync signal and will not affect the addressable
registers’ contents. Please see Page 27.