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Direct Digital Synthesis (DDS)
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AD9954: What is the relationship between the power consumption and the frequency of the system clock?
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Documents
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AD5930: FAQ
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AD5933: FAQ
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AD5934: FAQ
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AD9152: FAQ
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AD9830: FAQ
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AD9832: FAQ
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AD9833: FAQ
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AD9834: FAQ
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AD9835: FAQ
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AD9837: FAQ
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AD9838: FAQ
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AD9840: FAQ
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AD9840A: FAQ
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AD9845A: FAQ
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AD9850: FAQ
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AD9851: FAQ
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AD9852: FAQ
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AD9854: FAQ
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AD9854ASQ: FAQ
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AD9856: FAQ
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AD9857: FAQ
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AD9858: FAQ
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AD9910: FAQ
AD9912: maximum PFD frequency
AD9912: multichip synchronization
AD9912: Sync multiple devices
AD9914 - connection to an uC
AD9914 pahse wheel and spur relationship and synchronisation query
AD9914/AD9915 Programmable Modulus Mode Tuning Resolution
AD9914/AD9915 REFCLK Multiplier
AD9914/AD9915 SFDR Specification
AD9914/AD9915 Super Nyquist Zones
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AD9914: FAQ
AD9915 for best phase noise performance
AD9915/PCBZ user guide: where can I find it?
AD9945 addtion of Startup Register (PCN 11_0006). How to handle mixed stock of parts pre and post PCN
AD9951 - RefCLK using external Oscillator instead of Crystal
AD9951: Clock signal
ad9951: REFCLK input considerations
AD9951: REFCLK inputs
AD9952: Eval board
AD9952: Pin connection
AD9952: Pin connections
AD9952: Pin function of 47 and 48
AD9953: Crystal specification
AD9953: Design questions
AD9953: Generating a signal in the 50-90MHz range
AD9953: How to write RAM
Ad9953: Several issues
AD9954 phase/amplitude dithering
AD9954 power consumption on power down?
AD9954's output compliance voltage dependencies?
AD9954: DACP pin connected to AGND
AD9954: Effect of REF CLK
AD9954: RAM continuous recirculate mode, start phase information
AD9954: Spur at SYSCLK/4
AD9954: Synchronization of 16 AD9954
AD9954: What is the relationship between the power consumption and the frequency of the system clock?
AD9956 linear sweep (no dwell disabled) has a glitch when the FTW0 is changed to a lower value after a ramp-up
AD9956: Run-time error 13
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AD9957: FAQ
AD9958: Timing of SCLK for a data read operation
AD9959 evaluation board clock
AD9959: ADIsimDDS_spectrum
AD9959: FSK modulation performance
Ad9959: Oscillator
Bit 2 in address 0x0200 in I/O register - HSTL driver
Can I use a DDS to produce modulation waveforms?
Can I use the AD9859 without using external components to create a square wave?
Can the AD9957 Evalboard and software generate CDMA modulation of the AD99957?
Can you send me the AD9856 filter coefficients?
DDS Features Chart
DDS for space or Radiation Hard Specifications
DDS_harmonic or image phase adjustment
DIRECT DIGITAL SYNTHESIS (DDS) SUPPORT COMMUNITY
Documentation error: AN-1108 application note, AD9832 analog output on reset is incorrect
Does your DDS evaluation software work on Windows XP/Vista/7/8 32-bit/64-bit?
Eval kit for AD9951, AD9952, AD9953 and AD9954
Execution error 13 Type incompatible
FAQ: Are any of your DDS products space qualified?
FAQ: Are there any specific recommendations regarding via fill material in the circuit board for the thermally enhanced package styles associated with some ADI DDSs?
FAQ: DDS Tutorial - Introduction to DDS
FAQ: DDS Tutorial - SINC Envelope Correction
FAQ: DDS Tutorial - The Accumulator
FAQ: DDS Tutorial - The Angle-to-Amplitude Converter
FAQ: DDS Tutorial - The DAC
FAQ: DDS Tutorial - The DAC Reconstruction Filter
FAQ: DDS Tutorial - The DDS in Action
FAQ: DDS Tutorial - User Guide
FAQ: Do you recommend a linear or switching power supply?
FAQ: How does the REF CLK performance affect the DDS output performance?
FAQ: How often should I send an I/O_UPDATE when I write to multiple registers?
FAQ: Is there a relationship between the sample rate and the maximum update rate?
FAQ: Is there information available on proper soldering and assembly techniques for thermally enhanced packages?
FAQ: Learning more about Direct Digital Synthesis Technology (DDS)
FAQ: What does the programmable modulus feature provide?
FAQ: Why isn't the SFDR of my DDS with 14 bit DAC better than the SFDR of one with a 10 bit DAC?
FAQ: Why would I choose to use DDS for synthesizing a signal rather than a PLL?
general usage of the AD9850
How can I perform amplitude modulation using the AD9835?
How do ADI's DDS engines compare to FPGA-based DDS engines?
How to manually select the device driver used by the Evaluation software?
In most of DDSs’ datasheet, analog ground (AGND) and digital ground (DGND) pins are separate, but in most of the DDS evaluation boards AGND and DGND pins are not separated. Why?
Is Data Valid Time (tDV) of 12nS for AD9959 correct? Or should it be 1.2nS instead?
Is it okay to use a frequency modulated (FM) source as my clock input to the system clock of the DDS?
Is it possible to start a negative sweep using the digital ramp generator of the DDS?
Is the AD9914's EPAD internally connected to AGND or DGND?
Problems with Evalboard for AD5930, EVAL-AD5930EBZ
RE AD5933 Capacitance Measurement
Running the AD9914 faster than 3.5GHz
Sine wave generator
The AD9959's SYNC_CLK has no signal. What should I check to fix this?
the introduction document of AD9954 evaluation
Trouble programming AD5932 Evaluation Board
Under what conditions is it OK to use the on-board PLL multiplier?
What are the basic things to be checked when using the DDS evaluation board via external control?
What is the difference between the AD9914 and AD9915?
What is the function of the SYNC_IO pin on the DDS parts?
What kind of problems might I expect from exceeding the maximum clock rate?
What number would I write to the Phase Adjust Register to get for example 10 degrees?
What’s the function of the SYNC_CLK pin on the DDS?
Where can I find in the datasheet on how the output of the DDS will drift?
Why does a DDS need a reconstruction filter?
Why does my narrowband spectral performance degrade when using larger values of multiplication on the internal reference clock multiplier (PLL)?
AD9954: What is the relationship between the power consumption and the frequency of the system clock?
Q
What is the relationship between the power consumption and the frequency of the
system clock?
A
Please refer to the results in the attached file.
Attachments:
AD9954_Eval_Board_Current_Draw.xlsx
ad9954
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