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Direct Digital Synthesis (DDS)
Direct Digital Synthesis (DDS)
Documents AD9954: Effect of REF CLK
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    • AD9954: Effect of REF CLK
    • AD9954: RAM continuous recirculate mode, start phase information
    • AD9954: Spur at SYSCLK/4
    • AD9954: Synchronization of 16 AD9954
    • AD9954: What is the relationship between the power consumption and the frequency of the system clock?
    • the introduction document of AD9954 evaluation
  • +AD9956: FAQ
  • +AD9957: FAQ
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AD9954: Effect of REF CLK

Q 

What is the RELATIVE level of the DDS ""spurious"" at  DDS-Clock ( AD9954 at
400 MHz.) / 8 ,and DDS- Clock / 16 ?
( Ofcourse with no filtering but direct at R-DAC and single ended oputput )
Any measuremnts done ?
And are these spurious levels affected if output is done with broadband balun ?

 

A 

The DDS functions like a high-resolution frequency divider with the reference
clock as the input and the DAC as the output. The spectral characteristics of
the reference clock directly impact the spectral. characteristics of the DDS.
Any phase noise or spur on the reference clock will also appear at the DAC
output, but will be reduced in magnitude by the frequency division process. The
improvement is directly related to the ratio of input to output frequencies,
expressed as:

dB = –20 log(N)

where N is the ratio of the reference clock frequency to the output frequency.
Figure 2 shows phase noise improvement resulting from division of the reference
clock frequency. Residual phase noise should be just the phase noise added by
the DDS, but the contribution from the reference clock is not completely
eliminated. Here the reference clock is 300 MHz, with output frequencies of
5MHz (blue) and 80 MHz (red). The difference between the phase noise of 5 MHz
and 80 MHz at lower frequency offsets is 24 dB, as predicted by the equation
above.  This indicates that the inherent REFCLK path (internal / external) is a
significant contributor to the overall phase noise.

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