If we configure the 21st bit of CFR1 to 0, then the CCI_OVFL Pin was always
high; If we configure the bit as 1, then the CCI won't overflow. In normal
operation, should this bit be configured as 1?
If a CCI overflows exists, it could be due to....
1) A profile pin change while TxEnable is high. Don't let profile pins float.
2) Excessive jitter on the REF CLK.
The CCI clear bit can be set to clear a CCI overflow. Typically, this bit is
set to logic 0.
If this bit is set to logic 1 to clear a CCI overflow, it will automatically go
back to logic 0 and the user must set to logic 1 again if needed.