diagrams are very unclear. The falling edges do not point to the read data bits
properly. In table 25, the minimum data valid time is denoted to be 12ns (must
that be 1.2ns?).
In read mode, the bit is pushed out on the falling edge of SCLK. The first
falling edge is from the last SCLK for the instruction byte. However, there is
a minimum wait time (valid time) of 12ns that one should wait before reading
the bit after the falling edge.