The SYNC_CLK should be running by default in crystal REF CLK mode or in any
other REF CLK mode. However, the following three issues could be the problem.
1) An invalid REF CLK.
In crystal REF CLK mode, here are some things to check.
a) The crystal must be dc coupled (refer to Figure 35 in the datasheet RevB)
b) The crystal must be between 20Mhz and 30Mhz.
2)If the REF CLK multiplier (PLL) is used in combination with/without the
crystal, the VCO output may be in a dead spot. Therefore ensure the correct VCO
gain is set, depending on required frequency range (refer to Table 1 "Internal
VCO Output Frequency Range"). You can also bypass the PLL, to confirm if this
could be the issue.
3) Ensure that SYNC_CLK is not disabled (i.e bit 4 in Register FR1). Refer to
Table 28 in datasheet RevB).