Sequence to synchronize multiple DDS

The configuration sequence consists of 7 steps. The key point to get the NCOs aligned is changing the SLEEP and RESET bits at the same time in all devices. The RESET bit clears the NCO and the SLEEP bit freezes the clock. This allows writing the frequency and phase registers of each DDS separately. To write the control register simultaneously in both chips, the two FSYNC lines have to be asserted at the same time.

In the example command sequence, #DDS1 is configured to a frequency of 125 kHz and #DDS2 is configured to 250 kHz with the MCLK frequency being 16 MHz.

Command Sequence Explained

  1. Write 0x2180 to both #DDSs (CS1 and CS2 asserted at the same time)
    1. Bits DB15 and DB14 are set to 0, which selects the Control Register.
    2. Bits DB13 (B28) is set to 1. This allows a complete word to be loaded into a frequency register in two consecutive writes.
    3. Bit DB8 (RESET) is set to 1. This resets internal registers to 0, including the NCO, and sets the analog output to midscale.
    4. Bit DB7 (SLEEP) is set to 1. This bit disables the internal clock, preventing the NCO from increasing it's value. New frequency. phase and control words can be written to the part when the SLEEP1 control bit is active.
  2. Write 0x4000 to #DDS1 (only CS1 asserted)
    1. Bits DB15 and DB14 are set to 0 and 1, which selects the Frequency Register 0.
    2. The following 14 bits are the 14 LSBs of the frequency word: 0x0000 in this example. 
  3. Write 0x4080 to #DDS1 (only CS1 asserted)
    1. Bits DB15 and DB14 are set to 0 and 1, which selects the Frequency Register 0.
    2. The following 14 bits are the 14 MSBs of the frequency word: 0x0080 in this example. 
  4. Write 0x4000 to #DDS2 (only CS2 asserted)
    1. Bits DB15 and DB14 are set to 0 and 1, which selects the Frequency Register 0.
    2. The remaining 14 bits are the 14 LSBs of the frequency word: 0x0000 in this example.
  5. Write 0x4100 to #DDS2 (only CS2 asserted)
    1. Bits DB15 and DB14 are set to 0 and 1, which selects the Frequency Register 0.
    2. The remaining 14 bits are the 14 MSBs of data: 0x0100 in this example.
  6. Write 0xC000 to both DDSs (CS1 and CS2 asserted at the same time)
    1. Bits DB15, DB14 are set to 11, which selects Phase Register 0. Bits DB13 and DB12 are set to 00 since they are don’t care (X).
    2. The following 12 bits are the phase word: 0x000 in this case to have both DDSs starting with the same phase. To set a different starting phase for each DDS, this register must be written in separate transactions asserting the corresponding CS.
  7. Write 0x0000 to both DDSs (CS1 and CS2 asserted at the same time)
    1. Reset bit DB8 is set to 0. A signal appears at the output of the DAC seven MCLK cycles after RESET is set to 0.
    2. Sleep1 bit DB7 is set to 0. MCLK is enabled.
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