The AD9959's SYNC_CLK has no signal. What should I check to fix this?

Q The AD9959's SYNC_CLK has no signal. What should I check to fix this? A The SYNC_CLK should be running by default in crystal REF CLK mode or in any other REF CLK mode. However, the following three issues could be the problem. 1) An invalid REF CLK. In crystal REF CLK mode, here are some things to check. a) The crystal must be dc coupled (refer to Figure 35 in the datasheet RevB) b) The crystal must be between 20Mhz and 30Mhz. 2)If the REF CLK multiplier (PLL) is used in combination with/without the crystal, the VCO output may be in a dead spot. Therefore ensure the correct VCO gain is set, depending on required frequency range (refer to Table 1 "Internal VCO Output Frequency Range"). You can also bypass the PLL, to confirm if this could be the issue. 3) Ensure that SYNC_CLK is not disabled (i.e bit 4 in Register FR1). Refer to Table 28 in datasheet RevB).

Is Data Valid Time (tDV) of 12nS for AD9959 correct? Or should it be 1.2nS instead?

Q Data Valid Time (tDV) is indicated as 12ns minimum (refer to Table 25 On page 31 of the AD9959 RevB data-sheet. This can't be true with respect to the fast 5ns serial-data clock? Should it be 1.2ns instead? A 12nS is correct. This timing is for a read operation (Figure 42). Read operations were not designed for speed like the write operation. 12ns is what the designers targeted as the minimum.

Q Is the ballon a t Pin 8 & 9 required when using an oscillator to drive the inputs or is the ballon just used to accommodate the mismatch of the external clock input impedance on the Eval-board? A The Balun and the 50ohm resistor –these are for impedance matching on the input of the AD9959.Source termination across the cable for the ext clock for eval PCB. Also, the 50ohm source load termination does reduce the signal voltage level by 6dB, but this is inherent in any properly terminated transmission line. The alternative of leaving out the source termination resistor could lead to distortion or higher jitter.

AD9959: FSK modulation performance

Q I did an experiment of AD9959EVB. System Clock is 500MHz, FTW0 = 10MHz, FTW1 = 10.1MHz, use P0 Pin to switch the DAC's output frequency.When the switching time is 20us, then the DDS's output is like Figure 1. If the switching time is 2ms, then the DDS's output is Figure 2. The switching time longer, the performance better. So seems when DDS is used in Hop Frequency application, if the switching time shorter, the output signal's performance is worse. For DDS's quick hop frequency applications, do you have some advice which can increase the performance of output signal? A Is the profile pin toggle rate synchronous to the SYNC_CLK. Meaning, is the toggle rate and SYNC_CLK at an integer ratio. If not, that should help some. Note, the profile pin toggle rate directly impacts the modulation index. The modulation index will impact how the energy is spread in the spectrum. Attachments: AD9959_FSKmodulationperformance.docx

AD9959: ADIsimDDS_spectrum

Q Currently, we found the bandwidth of single tone output from frequency response in the ADIsimDDS tool is 800KHz. Pls see the attached. Is it all right for such wide bandwidth? Or is there something wrong with the software? Would you pls give some professional suggestion? Here is the ADIsimDDS link for you: http://designtools.analog.com/dtDDSWeb/dtDDSMain.aspx A The DDS tool was intended to be used to do frequency planning only, it should not be used to determine the frequency spread. Attachments: ADIsimDDS_spectrum.zip

AD9959 evaluation board clock

Q We are currently using an AD9959 DDS evaluation board. I am interested in clocking the system using the external quartz option. Could you please suggest an option for the quartz crystal? A We do not recommend a specific manufacturer, but Ecliptek, Epson, Vari-L, Connor-Winfield, Wenzel, and Valpey-Fisher are known as sources for high quality parts. The following application note may be of some help: http://www.analog.com/static/imported-files/application_notes/AN-419.pdf

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