the introduction document of AD9954 evaluation

Q how can I get the AD9954 evaluation software introduction. A please see the attachment. Attachments: AD9954evaluationsoftwareintroduction.zip

AD9954: DACP pin connected to AGND

Q The datasheet of the AD9954 specifies that DACBP should be decoupled to Ground. It would make sense to me to decouple it to the Analog Ground rather than the Digital Ground. It is not specified in the datasheet. Any more information about this ? A You are correct, the DACBP pin should be decoupled to AGND. We have used a 1uF capacitor on the AD9954 evaluation board. The schematic of the evaluation board is available on the AD9954 product page on our website.

AD9954: Effect of REF CLK

Q What is the RELATIVE level of the DDS ""spurious"" at DDS-Clock ( AD9954 at 400 MHz.) / 8 ,and DDS- Clock / 16 ? ( Ofcourse with no filtering but direct at R-DAC and single ended oputput ) Any measuremnts done ? And are these spurious levels affected if output is done with broadband balun ? A The DDS functions like a high-resolution frequency divider with the reference clock as the input and the DAC as the output. The spectral characteristics of the reference clock directly impact the spectral. characteristics of the DDS. Any phase noise or spur on the reference clock will also appear at the DAC output, but will be reduced in magnitude by the frequency division process. The improvement is directly related to the ratio of input to output frequencies, expressed as: dB = –20 log(N) where N is the ratio of the reference clock frequency to the output frequency. Figure 2 shows phase noise improvement resulting from division of the reference clock frequency. Residual phase noise should be just the phase noise added by the DDS, but the contribution from the reference clock is not completely eliminated. Here the reference clock is 300 MHz, with output frequencies of 5MHz (blue) and 80 MHz (red). The difference between the phase noise of 5 MHz and 80 MHz at lower frequency offsets is 24 dB, as predicted by the equation above. This indicates that the inherent REFCLK path (internal / external) is a significant contributor to the overall phase noise.

AD9954's output compliance voltage dependencies?

Q The limitation to AVDD +/-0.5V comes from the use of a transformer and the device itself. If I use a resistor the ouput compliance voltage windows will became AVDD to AVDD-0.5V ?so half of it? A The output voltage limitation is from the DAC itself. The DAC outputs should be terminated with the proper load impedance in order to limit the output voltage swing so that it is within the voltage compliance limits of the output stage. Both DAC outputs (true and complementary) should be terminated with the same resistance for best SFDR performance, and to limit harmonic distortion at higher output frequencies. In most cases this should be 50 ohms. Remember the output voltage compliance range is "AVdd +/- 0.5V". To calculate the peak to peak voltage at the complementary DAC outputs, simply multiply the full scale current by the equivalent output load. Note, the DAC outputs are open drain and must be dc terminated for current flow. Whatever output network is used (termination resistors + filter + transformer, etc) the equivalent load must be used for the peak to peak voltage (Vpp) calculation. Again, Vpp = full scale current * equivalent load. For instance, say there's two 50 ohm output termination resistors at the DAC driving a differential filter with a 100 ohms at the output of the filter. The equilvalent load at each DAC output is 25 ohms. Since the AD9954's DAC outputs are referenced to AVDD (current sinking DAC), not ground (current sourcing DAC), the output common mode voltage for both outputs is (AVDD - Vpp/2). Note, if the DAC outputs are terminated into a transformer or inductors referenced to AVDD, the DAC output will swing about AVDD. In that case, the common mode voltage is AVDD.

AD9954 power consumption on power down?

Q I would like to know what is the AD9954's power cunsumption for each state on powerdown (refer to Table 9 of the datasheet, Rev.B A Please see estimated results attached for the AD9954 power consumption in different powerdown modes. Recorded in this excel are the current consumption numbers for the powerdown of the other blocks of the AD9954YSVZ (CLK INPUT,DAC, COMPARATOR); this was done when the part had only a 400 MHz REFCLK with no output, and a 400 MHz REF CLK with a single tone of 160 MHz. Attachments: AD9954_powerdown_CURRENT_CONSUMPTION.xlsx

AD9954: What is the relationship between the power consumption and the frequency of the system clock?

Q What is the relationship between the power consumption and the frequency of the system clock? A Please refer to the results in the attached file. Attachments: AD9954_Eval_Board_Current_Draw.xlsx

AD9954: Synchronization of 16 AD9954

Q 1.Our design uses the two options described on datasheet page 30. I.e. synchronizing with SYNC_IN and SYNC_CLK signals AND a single crystal driving multiple (=16) AD9954s. Do you recommend using it this way? 2a.Datasheet section Synchronizing multiple AD9954s, wrote: … all units must share a common clock source. Weve one clock source but it is not common, right? Well it seems like that the original XTAL clock would be delayed by each AD9954. Is this right? The internal PLL of the AD9954 cannot compensate for this right? 2b.For an equal DAC output we should likely need to compensate for the REFCLK delay at AD9954 further away from the XTAL in the phase offset word. Do you think so? 3a.The alternative what comes to my mind is to use a PLL-based clock distribution chip to have the reference clock aligned to each AD9954 chip. Do you think this is a better idea? Do you think the headache described in 2b will disappear? 3b.In the case of using a clock distribution chip. Do expect the sole option of synchronizing 16 AD9954s with SYNC_IN and SYNC_CLK signals will work? A 1. I would have my reservations about driving as many as 16 AD9954s with a single crystal. For such a large number of devices I would be inclined to consider a full clock distribution strategy, using perhaps our AD9510 and AD9512 parts. The accumulated delay and jitter between parts number 1 and 16 may create additional issues that would be better avoided. The synchronization arrangements look to be exactly what is described in the datasheet, 2.a and b See answer 1. The delay but more so the jitter will kill the system performance. 3. I think that by directly clocking the AD9945 at the REFCLK frequency and by connecting the SYNC_CLO to the SYNC_IN pins, you will obtain the best performance and synchronization of all 16 devices.

AD9954: Spur at SYSCLK/4

Q I have used AD9954 as a clock reference, but in the output of DDS, one spur which frequency is N*Fxtal/4 (N is the PLL multiplier)exists, would you help me how to eliminate this spur. A The frequency that you refer to is equal to the SYNC_CLK signal - which is always SYSTEM CLOCK/4. Therefore the spur is likely to arise from crosstalk/coupling between the SYNC_CLK signal and the DAC output. If you don't need the SYNC_CLK signal you can disable the SYNC_CLK output by writing to bit 1 in the control function register. If you need the SYNC_CLK signal then you should - minimise the capacitive load attached to the SYNC_CLK output - re-examine the system grounding and power supply decoupling, to reduce as far as possible the ground impedance and the power supply impedance at high frequencies - re-examine the system layout to ensure that SYNC_CLK output signal is not routed close to the REFCLK signal (if the REFCLK is modulated by SYNC_CLK, this can create spurs in the output signal)

AD9954: RAM continuous recirculate mode, start phase information

Q In the RAM continuous recirculate mode, what is the phase information at the very beginning of each sweep cycle? Does the phase reset to 0 at the beginning of each sweep cycle? A The RAM can be configured to add a phase offset to the signal path. If so, the phase offset value in the RAM is added to the output phase of the phase accumulator. So, unless the phase accumulator is reset per each sweep, the initial phase would not be constant for each sweep. You could use the clear phase accumulator bits (CLRACC1 or CLRACC2) to clear the phase accumulator, if desired.

AD9954 phase/amplitude dithering

Porgrammable phase/amplitude dithering is listed in the AD9954 features on the front page of the datasheet, but nowhere in the datasheet is there a description of how to implement it, or what it does. Please provide some guidance. The AD9954 DDS core includes optional phase and/or amplitude dithering controlled via the CFR1<20:16> bits. During characterization, we found there to be little impact when using this feature, so we chose not to promote it heavily, but neglected to strip it from the features of the part. That said, the feature still exists, and here is what you need to know to check it out yourself: Phase dithering is the randomization of the state of the least significant bits of each phase word. Phase dithering reduces spurious signal strength caused by phase truncation by spreading the spurious energy over the entire spectrum. The downside to dithering is a rise in the noise floor. Amplitude dithering is similar, except it affects the output signal routed to the DAC. The AD9954 uses a 32-bit linear feedback shift register (LFSR), to generate the pseudo random binary sequence that is used for both phase and amplitude dither data. The LFSR will generate, at the dds_Clock rate, the pseudo random sequence only if dithering is enabled. The enable signal is the OR of the dithering control bits (CFR1<20:16>). Phase dithering is independently controlled on the four least significant bits of the phase word routed to the angle rotation function. That is, any or all of the phase word four least significant bits may be dithered or not dithered, controlled by the user via the serial port. Specifically, the CFR1<19> bit controls the phase dithering enable function of the phase word <16> bit for all four phase dither instances. The CFR1<18> bit controls the phase dithering enable function of the phase word <15> bit for all four phase dither instances. The CFR1<17> bit controls the phase dithering enable function of the phase word <14> bit for all four phase dither instances. The CFR1<16> bit controls the phase dithering enable function of the phase word <13> bit for all four phase dither instances. This enable function is such that if the bit is high, dithering is enabled. If the bit is low, dithering is not enabled. Amplitude dithering uses one control bit to enable or disable dithering on the output of all four angle rotation blocks. If the amplitude dither enable bit (CFR1<20>) is logic 0, no amplitude dithering is enabled and the data from the DDS core is passed unchanged. When high, amplitude dithering is enabled. This FAQ was generated from the following discussion: AD9954 phase/amplitude dithering

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