I have an AD9913 evaluation board and I'm trying to monitor the SYNC_CLK signal at the J2 connector.  There is no signal at this connector, just +1.8VDC.  I have also probed the SYNC_CLK pin at the AD9913 device and found the same result.  What should I expect to see for the SYNC_CLK signal at the J2 connector?  Is there a way to access the SYNC_CLK enable/disable bit from the evaluation board GUI?  Does the GUI default to SYNC_CLK enabled or disabled?

  • 0
    •  Analog Employees 
    on Aug 9, 2018 11:48 PM

    The AD9913 defaults to SYNC_CLK enabled (CFR1[19]=0, which is the enabled state).

    At power up (or following a RESET) the SYNC_CLK pin should be toggling at the system clock rate. It should be readily available at the SYNC_CLK connector (J2).

    Note there is a buffer chip between the AD9913 and the J2 connector. It may be damaged and loading down the SYNC_CLK signal.

    Unfortunately, there is not a control element in the GUI to turn SYNC_CLK on and off. However, you can do so via the DEBUG window, which is accessible via the VIEW drop-down menu (top bar).

  • Thank you for the response.  I removed the buffer chip and installed a jumper across the signal path.  I can now measure the SYNC_CLK at the J2 connector.