Hi i saw that all the measurements in the datasheet are noted after bypassing internal PLL. Can anyone share some results on HSTL and CMOS outputs with internal PLL enabled. It will be helpful to understand and compare. Also please share the results of CMOS with PLL enabled Aswell as with S-Divider enabled
Hi Jules.
I am using the AD9912 REVB EVAL board for the validation.
I am trying to generate the Wide band and Narrowband Frequency domain plots as mentioned in the datasheet. Here are some graphs i have generated. I also have attached the SYSCLK PLL setting for your reference.
Case-1
Carrier Signal: 399MHz , the plot is taken after implementing the spur killer / IDAC_FS:20mA DEFAULT
In the Figure 20 of the Data sheet , the SFDR is -69dBc which i could not achieve even after implementing Spur killer. I tried varying the DAC Full scale current from 20mA default to 8.6mA and 31.7mA, however the response is same. 1)Do you have any suggestion to improve the SFDR within 500MHz span?
When i increase the span of the spectrum to 1.5GHz, here is how the spectrum looks like. The harmonic levels are too high. I interesting thing i observed during the tuning of IDAC is that the Alias due to 2nd harmonic is reducing but that of the third one is very adamant
the plot is taken after implementing the spur killer / IDAC_FS:8.64mA
2)Could you share the spectrum results, covering the span up to 2GHz with same carrier frequency and same setting of SYSCLOCK. It will help me evaluate the Harmonics power level that is generated
Case-2
Carrier Signal: 98.6MHz , the plot is taken after implementing the spur killer / IDAC_FS:20mA DEFAULT
Figure 6 shows the SFDR of -67dBc whereas i was able to achieve only -10.3dBc even after trying to implement spur killer
Case-3 CMOS _100kHz
Spectrum i observed at CMOS port is very dense and filled with harmonics. For CMOS i have tried both 3.3V and 1.8V pull-up . Looks like the results are same. Also i have tried to generate the 100kHz signal by 20MHz, 40MHz and 100MHz DDS output and then configuring the S divider accordingly. However the results are same.
Carrier Signal: 10kHz , the plot is taken after implementing the spur killer / IDAC_FS:8.64mA and CMOS Pull-up:3V3
The SFDR with 1MHz span is only -10dBc
3) Is there any setting specifically to be made while using CMOS either in hardware or in software to have a clean spectrum. I have the requirement of SFDR of at least -60dBc till the 6th fundamental of carrier?
4) Also please generate the CMOS low frequency (preferably 8kHz) signals using the PLL and S-divider and share the results for my better understanding as i was not able to find any low frequency test results in the datasheet
Observations:
Jus out of curiosity, i increased the RSET resistor from 10K to 20K to reduce the IDAC_FS to 4.32mA. I used this setting in all the above cases. Seems like the power level of carrier signal at the output of HSTL and CMOS doesn't change much
5) I felt the 2 amplifiers in the output chain (Both CMOS and HSTL) are saturated. As in my most of the observations, the power level of third harmonic of the carrier was dominating, and the signal before FEEDBACK IN is very clean all the harmonics are well within -50-60dBc range. What is your suggestion on this?
Hi Jules.
I am using the AD9912 REVB EVAL board for the validation.
I am trying to generate the Wide band and Narrowband Frequency domain plots as mentioned in the datasheet. Here are some graphs i have generated. I also have attached the SYSCLK PLL setting for your reference.
Case-1
Carrier Signal: 399MHz , the plot is taken after implementing the spur killer / IDAC_FS:20mA DEFAULT
In the Figure 20 of the Data sheet , the SFDR is -69dBc which i could not achieve even after implementing Spur killer. I tried varying the DAC Full scale current from 20mA default to 8.6mA and 31.7mA, however the response is same. 1)Do you have any suggestion to improve the SFDR within 500MHz span?
When i increase the span of the spectrum to 1.5GHz, here is how the spectrum looks like. The harmonic levels are too high. I interesting thing i observed during the tuning of IDAC is that the Alias due to 2nd harmonic is reducing but that of the third one is very adamant
the plot is taken after implementing the spur killer / IDAC_FS:8.64mA
2)Could you share the spectrum results, covering the span up to 2GHz with same carrier frequency and same setting of SYSCLOCK. It will help me evaluate the Harmonics power level that is generated
Case-2
Carrier Signal: 98.6MHz , the plot is taken after implementing the spur killer / IDAC_FS:20mA DEFAULT
Figure 6 shows the SFDR of -67dBc whereas i was able to achieve only -10.3dBc even after trying to implement spur killer
Case-3 CMOS _100kHz
Spectrum i observed at CMOS port is very dense and filled with harmonics. For CMOS i have tried both 3.3V and 1.8V pull-up . Looks like the results are same. Also i have tried to generate the 100kHz signal by 20MHz, 40MHz and 100MHz DDS output and then configuring the S divider accordingly. However the results are same.
Carrier Signal: 10kHz , the plot is taken after implementing the spur killer / IDAC_FS:8.64mA and CMOS Pull-up:3V3
The SFDR with 1MHz span is only -10dBc
3) Is there any setting specifically to be made while using CMOS either in hardware or in software to have a clean spectrum. I have the requirement of SFDR of at least -60dBc till the 6th fundamental of carrier?
4) Also please generate the CMOS low frequency (preferably 8kHz) signals using the PLL and S-divider and share the results for my better understanding as i was not able to find any low frequency test results in the datasheet
Observations:
Jus out of curiosity, i increased the RSET resistor from 10K to 20K to reduce the IDAC_FS to 4.32mA. I used this setting in all the above cases. Seems like the power level of carrier signal at the output of HSTL and CMOS doesn't change much
5) I felt the 2 amplifiers in the output chain (Both CMOS and HSTL) are saturated. As in my most of the observations, the power level of third harmonic of the carrier was dominating, and the signal before FEEDBACK IN is very clean all the harmonics are well within -50-60dBc range. What is your suggestion on this?
Hi Jules.
I am using the AD9912 REVB EVAL board for the validation.
I am trying to generate the Wide band and Narrowband Frequency domain plots as mentioned in the datasheet. Here are some graphs i have generated. I also have attached the SYSCLK PLL setting for your reference.
Case-1
Carrier Signal: 399MHz , the plot is taken after implementing the spur killer / IDAC_FS:20mA DEFAULT
In the Figure 20 of the Data sheet , the SFDR is -69dBc which i could not achieve even after implementing Spur killer. I tried varying the DAC Full scale current from 20mA default to 8.6mA and 31.7mA, however the response is same. 1)Do you have any suggestion to improve the SFDR within 500MHz span?
When i increase the span of the spectrum to 1.5GHz, here is how the spectrum looks like. The harmonic levels are too high. I interesting thing i observed during the tuning of IDAC is that the Alias due to 2nd harmonic is reducing but that of the third one is very adamant
the plot is taken after implementing the spur killer / IDAC_FS:8.64mA
2)Could you share the spectrum results, covering the span up to 2GHz with same carrier frequency and same setting of SYSCLOCK. It will help me evaluate the Harmonics power level that is generated
Case-2
Carrier Signal: 98.6MHz , the plot is taken after implementing the spur killer / IDAC_FS:20mA DEFAULT
Figure 6 shows the SFDR of -67dBc whereas i was able to achieve only -10.3dBc even after trying to implement spur killer
Case-3 CMOS _100kHz
Spectrum i observed at CMOS port is very dense and filled with harmonics. For CMOS i have tried both 3.3V and 1.8V pull-up . Looks like the results are same. Also i have tried to generate the 100kHz signal by 20MHz, 40MHz and 100MHz DDS output and then configuring the S divider accordingly. However the results are same.
Carrier Signal: 10kHz , the plot is taken after implementing the spur killer / IDAC_FS:8.64mA and CMOS Pull-up:3V3
The SFDR with 1MHz span is only -10dBc
3) Is there any setting specifically to be made while using CMOS either in hardware or in software to have a clean spectrum. I have the requirement of SFDR of at least -60dBc till the 6th fundamental of carrier?
4) Also please generate the CMOS low frequency (preferably 8kHz) signals using the PLL and S-divider and share the results for my better understanding as i was not able to find any low frequency test results in the datasheet
Observations:
Jus out of curiosity, i increased the RSET resistor from 10K to 20K to reduce the IDAC_FS to 4.32mA. I used this setting in all the above cases. Seems like the power level of carrier signal at the output of HSTL and CMOS doesn't change much
5) I felt the 2 amplifiers in the output chain (Both CMOS and HSTL) are saturated. As in my most of the observations, the power level of third harmonic of the carrier was dominating, and the signal before FEEDBACK IN is very clean all the harmonics are well within -50-60dBc range. What is your suggestion on this?
