Post Go back to editing

DRG Programming Sequence

Category: Software
Product Number: ad9914

I am trying to use DRG mode of dds ad9914. However currently my output is nothing. Can anyone here guide me the correct step order to program the registers in DRG mode?

My current programming sequence:

Master_reset

Wait 20ms

CFR1: VCO calib enable, OSK enable, SDIO input only

IO update

CFR1: OSK enable, SDIO input only

CFR2: DIgitall ramp enable

CFR3: PLL enable

CFR4: PLL calib enable

IO UPdate

CFR4: Default value

Digital ramp lower limit

Digital ramp upperlimit

Rising Digital Ramp Step Size Register

Falling Digital Ramp Step Size Register

Digital Ramp Rate Register

IO Update

Then I change the DRCTL value every time there is a DROVER

My programming sequence is as above and my output is nothing, can anyone with experience tell me the correct programming sequence?



.
[edited by: HungHo at 8:11 AM (GMT -5) on 28 Feb 2025]