SPI configuration issue

Question

This board uses the 3 wire serial programming mode, io update pin, single tone mode , external reference clock, the 3 profile pins at low . 
 1- : 5 registers are written : cfr1 , cfr2, cfr3 , aux, profile register 0x0e 
 the sequence : mst_reset , chip select , cfr1 write on sdio : address 00 + 4 bytes + io update . similar for cfr2,3,aux. Profile register address 0x0e + 8 bytes + io update 
 2- 4 registers are read back : cfr1, cfr2 , cfr3, aux . for cfr1 , write 0x80 on sdio + io update . read 4 bytes on sdo . similar for cfr2,3, aux 
 the values read back for cfr1 & cfr2 are the same as written. The cfr3 & aux are different from written. 
 the timing diagram is available in the saleae format file for detailed view, but is rejected by this editor. A Screen capture is provided 
 Any hint of what is wrong here? is there some limitation on the part state machine ? Or maybe a defective part? 
 thank you for your help 
 Henri

Henri · Accepted Answer

update: looking more carefully at the specific bits that were not read as written, they are called open. That is not defined for writing to. Avoiding tampering with those helped : writing the same value as in the state they were found at reset . A further improvement was noting a old post on this forum from feb 2015. Writing 2 io updates after each writes to a register appeared to help on being able to read back correctly register 0x0e that is 64 bits. An earlier problem was that it read back only part of the bits. Also, It appears that setting some of the "open" bits was forcing some of the other bits in that register to change to values that were not desired for normal operation. Avoiding changing the open bit values by writing to them was beneficial in this case. The analog output still needs to be checked for accuracy)

Henri · Answer

update: the sync clk is now visible and the dds output signal at the expected frequency programmed 
 where the datasheet needs to improve: Auxiliary DAC Control Register Address 0x03 [7:0] p 58 : the default appears to be 0x7f not 0xff . attempt to write the full scale value only result in 0x7f being stored? This is a lower power output and maybe better for intermodulation? Another area of improvement : better diagrams for the sequence of reset pin , io reset, io update , data . I did not investigate further if the double io update is really required as time is limited i just left it in and need to go on with the remainder of this board bring up.

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SPI configuration issue

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