Issues in synchronising multiple AD9850 to maintain phase coherence during sweep mode.

Hi all,


For a current project, I need to generate at least 5 sine waveforms of the same frequency with a coherent phase relationship. This is required both during normal operation (fixed frequency) and while sweeping the frequency.

• Sweep Requirements:
  • Frequency Range: 10kHz to at least 3MHz
  • Sweep Speed: Variable, from a few hundred microseconds to tens of milliseconds, depending on the frequency step size.
• Implementation:
  • I'm using 5 AD9850 DDS chips.
  • Following the AD application note (AN-587), I'm using a 125MHz crystal reference clock distributed evenly and shielded to each DDS.
  • My current setup adheres to the diagrams below.
  • As recommended in the application note, I implement a common Main reset before data transfer to ensure phase coherence.
• Observed Issue:
  • Phase coherence is only maintained for sweep times of 500ms or longer across the 10kHz to 3MHz range.
  • Slower sweeps (sub-500ms) result in a loss of phase coherence.
  • During normal operation (fixed frequency), phase coherence is maintained.
  • However, during sweeps:
• Question:
  • Has anyone encountered similar issues with the AD9850 during frequency sweeps?
  • Are there any known techniques or workarounds to improve phase coherence during faster sweeps?
  • Is the AD9850 inherently suited for coordinated sweeps with multiple DDS chips?
• Code Snippet:
  • Main loop:
    
    
    void loop() {

    
    

      digitalWrite(RESET_G1, LOW);

      digitalWrite(RESET_G1, HIGH);

      digitalWrite(RESET_G1, LOW);

    
    

     for (unsigned long int freq = 10000; freq <= 500000; freq += 10000) {

       setFrequencyAndPhase(freq,0);

      //Debugging: Print the updated frequency

       Serial.print("Frequency set to: ");

       Serial.println(freq);

        //Wait for 1 second before the next frequency step

        delay(500);

       }

    
    

    }
    
    

    void setFrequencyAndPhase(unsigned long int freq_in_DDS, unsigned char phase_in_DDS) {

        // Calculate the 32-bit frequency word

        unsigned long freq_DDS1 = freq_in_DDS1 * 4294967295.0 / 125000000.0;

    
    

        // Calculate the 5-bit phase word

        unsigned char phase_word_DDS1 = (phase_in_DDS1 / 360.0) * 32.0;

    
    

        // Clear signals

        digitalWrite(W_CLK_DDS1, LOW);

        digitalWrite(W_CLK_DDS2, LOW);

        digitalWrite(W_CLK_DDS3, LOW);

        digitalWrite(W_CLK_DDS4, LOW);

        digitalWrite(W_CLK_DDS5, LOW);

        digitalWrite(D7LOAD_DDS, LOW);

        digitalWrite(FQ_UD_1, LOW);

    
    

        // Send all 40 bits (LSB first)

        for (int i = 0; i < 40; i++) {

            if (i < 32) {

                // Send frequency word (32 bits, LSB first)

                digitalWrite(D7LOAD_DDS, bitRead(freq_DDS, i));

            } else if (i < 35) {

                // Send control bits (3 bits, LSB first: typically all 0 for normal operation)

                digitalWrite(D7LOAD_DDS, LOW);  // Adjust control bits here if needed

            } else {

                // Send phase word (5 bits, LSB first)

                digitalWrite(D7LOAD_DDS, bitRead(phase_word_DDS, i - 35));

            }

            // Clock pulse

            digitalWrite(W_CLK_DDS1, HIGH);

            digitalWrite(W_CLK_DDS2, HIGH);

            digitalWrite(W_CLK_DDS3, HIGH);

            digitalWrite(W_CLK_DDS4, HIGH);

            digitalWrite(W_CLK_DDS5, HIGH);

           

            digitalWrite(W_CLK_DDS1, LOW);

            digitalWrite(W_CLK_DDS2, LOW);

            digitalWrite(W_CLK_DDS3, LOW);

            digitalWrite(W_CLK_DDS4, LOW);

            digitalWrite(W_CLK_DDS5, LOW);

           

        }

    
    

        // Latch data with FQ_UD

        digitalWrite(FQ_UD_1, HIGH);

     

        digitalWrite(FQ_UD_1, LOW);

       

    }

I appreciate any insights or suggestions the community can offer.

The overall setup follows the AN-587, I added three more DDSs.,
I am programming them in serial mode as opposed to parallel.