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Understanding Limitations

Category: Hardware
Product Number: AD9016

Hi,

I am using an AD9106 to generate two sine waves. One signal is static and the other that's given a phase shift and referenced against the static signal. I am very new to the AD9106 and trying to understand what I can and cannot do. I did NOT design the board the AD9106 sits on nor part of it's selection. It is a waveform4 click board by MikroE. I know that MikroE is 3rd party and I'm not asking for troubleshooting on the hardware. But I know someone will ask for the schematic so that's what I'm using. I can only imagine that the layout is a typical or suggested layout as MikroE products are hobbyist focused.

My end goal is to give the sine waves a DC offset so that there's no negative component, i.e., if I have a 1.0 Vpp sine wave, I want to give it a +0.5 Vdc offset. I see that the chip has the DACxDOF registers which I am able to modify. However the signal I see on my o-scope doesn't line up with what I would expect. For example, if I set the DACxDOF register with a value of 0x7FF, which says it's an offset of 0.5, the the top half of the output sine wave is cut off. Reading through the datasheet, on page 26, under the DACx Digital Offset Summer, it says, "if the resulting DAC input code...exceeds full-scale, the output is clipped at IOUTFSx", and I think this is what's happening.

Okay so IOUTFSx must be clipping my signal. Let's figure out what that value is. Looking at the schematic I provided, we're using the internal voltage reference of 1.04 V (REFADJ = 0x0000). All the RSET registers are using the default value (0x0A) which is 8 kΩ. Using equations 3 & 4 in the datasheet, we have:

  • IREFx = VREFIO / RSETx
  • IOUTFSx = 32 x IREFx

IREFx = 1.04 V / 8 kΩ = 0.13 mA

IOUTFSx = 32 x 0.13 mA = 4.16 mA

All this is fine, and I think I'm performing the calculating correctly, but I don't have a load on the output. It shouldn't be exceeding IOUTFSx and thus shouldn't be clipping.

If none of this is possible with the AD9106, I am able to use an external circuit to give the signal the DC offset I'm looking for. However, software would be easier.

Side note, what does a digital offset of 0.5 mean? There's no units with it. I assume it means a positive shift of half the output. 0x400 would be a positive shift of a quarter of the output. That's another question.

Thank you.

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  • Hi  ,

    Apologies for the delayed response. We're currently looking into this and we'll get back to you in a few days. Just a quick question, do you also have the AD9106 Evaluation Board with you? 

    Best regards,
    Marco

  • Hi mattdrsbh,

     

    As mentioned on page 26 of datasheet, if the resulting DAC input code with the digital offset exceeds full-scale, the output is clipped at IOUTFSx.  This will be the same with DACx Digital Gain.
    • Underlined in blue is the answer on your side note.  0.5 is the 50% of the DAC output current.
     
     
     
    The output clipping at IOUTFS is a safeguard to ensure that the DAC operates within its designed range and prevents potential issues due to excessive input codes.
    Mathematically, this can be described using the following steps:
     
    • DAC Input Code: Represented by a digital value.
    • e.g. DAC Input Code = 3000 (7D0); DC Offset = 2047 (7FF)
     
    • Full-Scale Current: The full-scale output current, IOUTFSX, is the maximum output current that the DAC can produce.
    • e.g.  VREFIO = 1.04 V; RSET = 8 kΩ
     
    • Conversion Equation: The ideal output current IOUT from the DAC, before clipping, is given by:
    • e.g. IOUTP
    • IOUT < IOUTFS; No clipping
     
    • Clipping Condition: If the DAC Input Code exceeds the value that corresponds to the full-scale range, the output current is clipped at IOUTFSX. This can be expressed as:
    • IOUT > IOUTFS ; Clipping at DAC output.
     
    To prevent DAC (Digital-to-Analog Converter) output clipping, consider these approaches:
    • Adjust the Input Signal:
      • Reduce Amplitude: Lower the amplitude of the input signal to ensure it stays within the DAC's full-scale range.
      • Amplification Control: Apply controlled gain to the input signal to ensure it stays within the DAC’s acceptable range.
    • Increase DAC Resolution:
      • Higher Bit DAC: Use a higher resolution DAC (more bits) to increase the dynamic range.
    • Larger Full-Scale Range:
      • Adjust RSET value:  Lower the value of RSET use.
      • Higher Full-Scale Current: Select a DAC that supports a larger full-scale output current or to accommodate higher input signals.
    Thanks and kind regards,
    Alex
  • Hi Alex,

    Thank you for taking the time to read my post and provide an answer. I do appreciate it. I unfortunately had to pivot in the design due to technical issues beyond the questions I asked. I have saved this information so I can reference it next time.

    Also I don't have the eval board, but I will get one. You are not the first person to ask me that.I get the impression being able to play around with one will allow me an easier path to troubleshoot any issues I run into.

    Thanks again.