Programming DDS using FPGA

Hi srinathpatti ,

Can you tell me what your specific application is? What your input clocks, expected DDS output, and waveform you wanted to achieve. Thanks.

All the best,

Jules

Hi Jules,

We are developing a phased array. So we need precise phase control between the four channels.
We need single tone mode of operation at 54 MHz.
Input clock is 25 MHz and multiplication factor is 20x (System clock is 500 MHz)

I am using U2 header on EVAL board. I connected the PWR_DWN to GND and other pins (Reset, IO_update, SDIO_0, CSB, SCLK) to FPGA. Currently, I am not using SYNC clock.

With Regards,

Srinath

Hi srinathpatti ,

Just checking if you happen to remove jumpers for manual control as shown below:

Also make sure J10 is supplied with 1.8V. 

Just checking if you might have missed this frequently disregarded steps. 

All the best,
Jules

HI Jules,

The following is the setup on EVAL board

This is the output from DDS seen in Oscilloscope:

I have followed this programming sequence: (Images from Logic analyzer)

Total sequence:

Initialization:

Frequency Tuning Word, Remaining registers and IO update

With Regards,

Srinath

Hi,

I have resolved this issue by combing through forum

ez.analog.com/.../ad9959-unused-pins-io_update