Hello,
Is there a fixed phase relationship between the external REFCLK and the PLL generated SYNC_CLK?
I'm curious if I can drive the profile pins based on REFCLK vs SYNC_CLK since this clock directly drives a PLL on my FPGA.
Thanks,
Joshua
AD9959
Recommended for New Designs
The AD9959 consists of four direct digital synthesizer (DDS)
cores that provide independent frequency, phase, and amplitude
control on each channel. This...
Datasheet
AD9959 on Analog.com
Hello,
Is there a fixed phase relationship between the external REFCLK and the PLL generated SYNC_CLK?
I'm curious if I can drive the profile pins based on REFCLK vs SYNC_CLK since this clock directly drives a PLL on my FPGA.
Thanks,
Joshua