Issues generating 4 DDS sine waves on the AD9106 with independently variable amplitude, phase, and frequency: Repost

Hi Vishwanath ,

Great to hear that the issues with DAC2 has been resolved! However, I still find it peculiar that your amplitude and phase of your output is varying depending on your frequency. What is your DAC CLK frequency and what frequency are you generating out of the DAC? 

Since you are using EVAL-AD9106, please check if the frequency is within the bandwidth of the baluns in the clock and DAC outputs in the EvB. The baluns will need to be bypassed as mentioned in my reply in the earlier post, especially since you want to generate low frequencies (~Hz range). You could try generating frequencies in the kHz range first (e.g. generate a 5kHz-50kHz sine wave using a 1 MHz DACCLK), then connect the DAC outputs to the on-board Op-amps. This worked on my end using the EVAL-AD9106 without any variation in the phase/amplitude of the waveform while the output frequency is varied. If it is varying, there might be a problem with your Arduino code. You could use the sample MBED codes (found under "Software Needed" section in this link) as reference for your Arduino code.

Best regards,
Marco

Hello Marco, 

We have not yet connected an external clock to the EVAL board, so we are just using the on-board crystal oscillator for a DAC CLK frequency of 156.25MHz. For a set DGAIN, we observe fluctuations of 1 mV between 0 and 100kHz and around 15 mV from 100kHz to 3Mhz when observed on a lock-in amplifier. We mostly attributed the phase fluctuations to errors with our measuring system.

You mentioned in your previous post that the clipping we observed is not related to the current limiting of the output. Do you know what could be causing it in that case? For each of the DACs on the new board, we still see clipping of the sine wave with gain factors above a magnitude of 1. For example, past a DGAIN of 0x4000 we see a flattening of the top and bottom of the sine wave.

Are there any additional resources, besides your post, on configuring an external clock for the EVAL-AD9106? The AD9106 datasheet itself doesn't cover the baluns that have to be bypassed.

Also, I wasn't able to find the Evaluating the AD910x using Mbed article link you just posted on the EVAL board documentation page. Is there another documentation page that I should be looking at?

Thanks for the help, 

Vishwanath

Hi Vishwanath ,

Apologies for the confusion. Do you mean the observation below? I generated a sample 50kHz sinusoid generated from SRAM using a DACCLK of 156.25 MHz. The clipping observed in the oscilloscope is due to the compliance range of AD9106, which is limited from -0.5 to +1V (Refer to page 5-6). AD9106 nominally gives a FSC of 4mA, and with the 250Ω load resistance connected in the EvB, this gives a voltage of +1V. Increasing the value in DACx_DGAIN amplifies the digital data coming out of the data, but the current out of the AD9106 is limited to 0 to IOUTFS. Increasing the DAC gain even further ahead of 0x4000 clips the DAC because it exceeds compliance. Do you require an output signal that exceeds 1V?

The EVAL-AD9106 has a provision for external clock, which is specified in the Wiki user guide (AD9106 & AD9102 Evaluation Boards [Analog Devices Wiki]). AD910x was originally designed for ultrasound applications (which operate in the ~MHz range) thus the EvB solution was designed that way with the baluns. Bypassing the baluns in the CLK and DAC outputs would be required if the part will be operated in the lower frequencies (~Hz range). 

The page Evaluating the AD910x using Mbed can be found by going to the "Quick Start Guide" section in the Wiki User Guide: AD9106 & AD9102 Evaluation Boards [Analog Devices Wiki]. The link to this Wiki User Guide can be found in AD910x-ARDZ-EBZ User Guide in the "Documentation and Resources" section.


Best regards,
Marco

Hello Marco, 

It's good to know that the clipping we observed is expected. We won't need more than 1V of output voltage. 

Thanks for pointing out the resources on clocking. 

Do you have any recommendations on how we could achieve higher precision in our amplitude control? Right now, by adjusting the DGAIN registers, we have a precision of around 0.5mV since we are limited to 0x4000 and below. We would like to have much tighter control of the output voltage.

Thanks, 

Vishwanath