AD5934 performance compare to AD5933

There is some impact on impedance accuracy when the sampling rate is reduced but it is difficult to quantify since it depends on multiple factors, including the nature of the impedance being measured.

I am attaching a simulation model that includes the ADC and the DSP so that you can evaluate the degradation in your particular use case.

EVAL-AD5933 with ADC.asc

LTSpice does not have a way to display numerical results, so the outcome of the formulas that emulate the DSP can be seen in the Error Log file.

re: INTEG(v(imeas)*v(sin))=9.81017e-005 FROM 0 TO 0.0002
yreal: (2*re*freq)/(n*gain*rfb)=0.000981017
im: INTEG(v(imeas)*v(cos))=3.58174e-006 FROM 0 TO 0.0002
yim: (2*im*freq)/(n*gain*rfb)=3.58174e-005
zmod: 1/sqrt(yreal**2+yim**2)=1018.67
phi: atan(yim/yreal)=2.09097
zre: zmod*cos(phi)=1017.99
zim: zmod*sin(phi)=37.1674

Hi,

Circuit: * C:\Users\galya\Downloads\EVAL-AD5933 with ADC.asc

WARNING: Node N008 is floating.

WARNING: Less than two connections to node N008.  This node is used by A1.
WARNING: Less than two connections to node COS.  This node is used by V5.
WARNING: Less than two connections to node IMEAS.  This node is used by E3.
Instance "m:u2:6": Length shorter than recommended for a level 2 MOSFET.
Instance "m:u2:5": Length shorter than recommended for a level 2 MOSFET.
Instance "m:u2:4": Length shorter than recommended for a level 2 MOSFET.
Instance "m:u2:3": Length shorter than recommended for a level 2 MOSFET.
Instance "m:u2:2": Length shorter than recommended for a level 2 MOSFET.
Instance "m:u2:1": Length shorter than recommended for a level 2 MOSFET.
Instance "m:u1:6": Length shorter than recommended for a level 2 MOSFET.
Instance "m:u1:5": Length shorter than recommended for a level 2 MOSFET.
Instance "m:u1:4": Length shorter than recommended for a level 2 MOSFET.
Instance "m:u1:3": Length shorter than recommended for a level 2 MOSFET.
Instance "m:u1:2": Length shorter than recommended for a level 2 MOSFET.
Instance "m:u1:1": Length shorter than recommended for a level 2 MOSFET.
Direct Newton iteration failed to find .op point.  (Use ".option noopiter" to skip.)
Starting Gmin stepping
Increasing initial diagonal Gmin to 100
Increasing initial diagonal Gmin to 1000
Gmin = 1000
Gmin = 107.374
Gmin = 11.5292
Gmin = 1.23794
Gmin = 0.132923
Gmin = 0.0142725
Gmin = 0.0015325
Gmin = 0.00016455
Gmin = 1.76685e-005
vernier = 0.5
vernier = 0.25
vernier = 0.125
vernier = 0.0625
vernier = 0.03125
vernier = 0.015625
vernier = 0.0078125
Gmin = 1.13078e-005
vernier = 0.00390625
vernier = 0.00195313
vernier = 0.000976563
vernier = 0.000488281
Gmin = 0
Gmin stepping failed

Starting source stepping with srcstepmethod=0
Could not converge to DC with sources off!
Starting source stepping with srcstepmethod=1
Source Step = 3.0303%
vernier = 0.25
Source Step = 7.57576%
Source Step = 15.1515%
Source Step = 22.7273%
Source Step = 30.303%
Source Step = 37.8788%
vernier = 0.0625
Source Step = 37.1419%
Source stepping failed

Pseudo transient terminated at 102.851 s, solution accepted ready or not!

re: INTEG(v(imeas)*v(sin))=-4.85799e-011 FROM 0 TO 0.0002
yreal: (2*re*freq)/(n*gain*rfb)=-4.85799e-010
im: INTEG(v(imeas)*v(cos))=7.34091e-011 FROM 0 TO 0.0002
yim: (2*im*freq)/(n*gain*rfb)=7.34091e-010
zmod: 1/sqrt(yreal**2+yim**2)=1.136e+009
phi: atan(yim/yreal)=-56.5046
zre: zmod*cos(phi)=6.26926e+008
zim: zmod*sin(phi)=-9.47348e+008


Date: Thu Jul 11 09:03:33 2024
Total elapsed time: 8.321 seconds.

tnom = 27
temp = 27
method = modified trap
totiter = 61738
traniter = 46503
tranpoints = 23251
accept = 18907
rejected = 4560
matrix size = 315
fillins = 552
solver = Normal
Thread vector: 105.9/45.5[8] 19.8/10.7[8] 15.4/8.2[7] 3.1/20.3[1]  2592/500
Matrix Compiler1: 37.73 KB object code size  33.2/15.9/[4.6]
Matrix Compiler2: 37.53 KB object code size  14.6/14.7/[6.0]

Thank you for answering.

Is there delay in the measurment time comparing to AD5933?,because of the change in the ADC sampling rate? 

I could not run the stimulation in the LTspice software, error log is attached.

Best regards,

Gal 

Hi,

Thank you for answering.

Is there any effect on the measurment time? 

I run the simulation in LTspice,but I got results that does not make sense.

re: INTEG(v(imeas)*v(sin))=-4.85799e-011 FROM 0 TO 0.0002
yreal: (2*re*freq)/(n*gain*rfb)=-4.85799e-010
im: INTEG(v(imeas)*v(cos))=7.34091e-011 FROM 0 TO 0.0002
yim: (2*im*freq)/(n*gain*rfb)=7.34091e-010
zmod: 1/sqrt(yreal**2+yim**2)=1.136e+009
phi: atan(yim/yreal)=-56.5046
zre: zmod*cos(phi)=6.26926e+008
zim: zmod*sin(phi)=-9.47348e+008

Thanks,

Gal

Note that the admittance values are very small, which means that the measured signal is very low (check Imeas). The RFB resistor must be set to the lowest impedance under test if using PGA gain 1, or 1/5 of it if using PGA gain 5.

Settling time remains the same because it is measured in cycles of the excitation signal, but measurement time is increased times 4 because the DSP still collects 1024 samples.

Hi,

Thank you,now the simulation is working.

I added a cite from the datasheet of the component, in both AD5934 and AD5933 is written the same, is it a mistake?

"The ADC takes 1024 samples, and the result is stored as real data and imaginary data in Register Address 0x94 to Register Address 0x97. The conversion process takes approximately 1 ms using a 16.777 MHz clock"

Should the conversion process be 4ms in AD5934?

Gal

I think so, but I don't have a board at hand to confirm it.

I tested the simluation in LTspice with 250k,1M,2M sps.

The simulation time is increased from 250k with 4.6 sec to 7 sec with 1M.

Then the measurment time decreases, is it a good way to test it?

Thanks,

Gal

Simulation time is not related to the operation time of the chip. 1 MSPS takes longer to simulate because there are more sampling points to process and the CPU is the same.

Yes, the AD9834 takes longer to perform the measurement than the AD9833.