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AD9959 Profile Pin Driver

Category: Hardware
Product Number: AD9959

Using the AD9959 to generate a 5.115MHz BPSK modulated carrier using the profile pins. Judicious selection of SYS_CLK ( 327.36MHz ) allows an integer relationship between modulation at 1.023MHz and the 5.115MHz. By adjusting timing delays this has achieved a close to zero crossing waveform from all 4 channels. However, close observation of the modulated signal shows intermittent non-zero crossing, Profile pin transitions meet the set-up  times WRT to the SYNC_CLK but very close examination shows that a negative going transition of the profile pin can result in an early non-zero crossing by one SYNC_CLK cycle. Positive going always seems OK.

Other forum entries suggest the profile pins should be driven by an AND gate with one input being the SYNC_CLK. This clearly gurantees the setup time, at the cost of  one SYNC_CLK delay, making the overall latency for the phase change SYS_CLK times 29 ( see data sheet) plus one SYNC_CLK.

Is this the correct solution?

John Newell

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