Hello,
In our design, we use an AD9915 with an FPGA. However, due to some limitations, we could not route the SYNC_CLK output to the FPGA. The AD9915 is clocked by a clock chip at 2.5GHz and the SYNC_IN is also connected to another output of this clock chip. SYNC_IN is a pulse gated from a 19.53MHz ( 2.5GHz/128) clock so the rising edge of this pulse always aligns with a rising edge of the 2.5GHz. The FPGA is clocked by another output of this chip at 78.125MHz (2.5GHz/32) and this clock is also aligned to the SYNC_IN pulse.
The diagram below illustrates how the edges are aligned. The frequencies illustrated are just to convey the idea of how the edges will align, not the exact frequency divisions.
This setup is not at all ideal but we have to do with it. In order to constrain the design, we assume that the SYNC_CLK generated by the DDS is in phase with the FPGA ref clock after the SYNC procedure is done using the SYNC_IN signal. However this proves to be complicated since we can't find any information about the SYNC_CLK delay related to the SYNC_IN pulse.
Is there any information on this?
