Ad9174 NCO frequency tuning issue

Hi,

I suggest you do following changes:

- I assume you selected only AD917x chip to configure under eval system option. You should select both AD917x and HMC7044 so both chips are configured when you hit apply.

- HMC7044 cannot generate DAC frequency of 5.8x GHz when used as direct clock (PLL OFF). You can select reference clock (PLL ON) as AD917x clock source under board clock setting so HMC7044 generates reference clock for DAC PLL and DAC PLL generates DAC clock frequency of 5.8x GHz .

Hope this helps.

Regards

Hi,

Thanks for the response

As previously mentioned, upon configuring the HMC and AD9174, the output is observed to be in accordance with the expected results

If you could kindly furnish the source code associated with the hex file AD9174_2D00_FMC_2D00_EBZ-RevC-eeporm-_2800_April-18_2900_.zip attached, it would greatly facilitate our understanding and implementation process

We are currently seeking guidance on the implementation of USB Human Interface Device (HID) in a AD9174 Evaluation board. If available, could you kindly share any pertinent code examples to aid in our development process?

Awaiting your response.

Hi,

Unfortunately I am not able to find any HID example code for AD9174.

Regards

Hi,

Thanks for the response

The primary objective of the AD9174 implementation is to generate frequencies spanning from 2 to 3.5 GHz with minimal phase noise while operating in direct digital synthesis (DDS) mode, (no JESD204B).

Based on the AD9174 datasheet, employing the direct clock method yields better performance in terms of phase noise minimization compared to utilizing the AD9174 PLL when operating in DDS mode.

In order to achieve our desired frequency generation and phase noise performance, we have outlined the following activities. Please provide your feedback on these plans

1. Upon reviewing the schematics, we have determined that the following modifications are necessary to provide the clock input through the J34 SMA connector. These modifications involve routing capacitors C34 and C35 to the external clock input and bypassing the HMC component. Is this correct?

2. Since the CLK IN is direct, does this mean we don't need to write any programming to the HMC7044?

3. What is the input frequency that needs to be provided to Connector J34 in order to generate 3.5 GHz using the AD9174 in DDS mode?

Awaiting your response

Hi,

As you plan to connect an external direct clock source to the AD9174, remove C36 and C38 and populate C34 and C35 instead so CLK± pins of the AD9174 are disconnected from HMC7044 and connected to J34. HMC7044 is not used in this case. Connect a high-performance clock with >=12dBm output level to J34. This is the only clock needed when using the AD917x in NCO-only mode.

You can use main NCO to generate frequencies spanning from 2 to 3.5 GHz. The DAC clock is at least 7GHz = 2 x 3.5GHz (max main NCO freq)  

Regards 

Hi,

Thank you for your update.

As per your recommendation, we set the CLK in at 7.2GHz and performed the necessary hardware rework. However, we are encountering an issue where multiple frequencies are being generated, each with a similar power level, but they do not align as exact multiples of the input frequency.

We have thoroughly checked the input clock before feeding it and ensured that the CLK IN and OUT is clean and noise-free, maintaining the same frequency. We also experimented with various ACE configurations, including different interpolation settings, but the issue persists.

I have attached a document containing the following information for your review:

1. ACE configurations used.
2. Measurements of CLK IN and CLK out.
3. Frequencies generated when feeding 2GHz and 2.5GHz inputs.

Also, I have included the registers read and write data captured using Wireshark. This information has been extracted and recorded in an Excel spreadsheet for your reference.

Please assist in identifying the cause of this discrepancy and provide guidance on potential solutions.

PDF

XLSX

Regards,

Chandan

Hi s.ilke ,

Kindly provide your feedback on the above query.. 

Regards,

Chandan

Hi,

What you observe might be the signal images in higher Nyquist zones. Can you please attach a screenshot of frequency spectrum measured at DAC output? It would be nice if you can put markers see the frequency and power level of larger tones. 

A screenshot of frequency spectrum of input clock would also be helpful.

Thanks

Hi s.ilke ,

Earlier attached PDF has the DAC 0 output measured. However i am providing a new document with screenshots of the frequency spectrum measurements. The signal measurements were conducted with a spectrum span of 14.9GHz.

The DAC 0 output was measured for NCO frequencies of 2.5GHz and 3.5GHz.

PDF

Looking forward to receiving your feedback.

Regards,

Chandan

Hi,

What you observe is the desired output (Fout) in 1st Nyquist zone and its image in 2nd Nyquist zone (Fs-Fout). Their amplitude is determined by DAC's sync function. See below.

If Fout is close to Nyquist frequency of Fs/2, the desired output and its first image become close to each other and have similar attenuation by the sync function.

If the sample frequency Fs is increased, the desired output and its first image move away from each other so the desired output will have less attenuation by the sync function and be higher in amplitude and the first image will have more attenuation by the sync function and be lower in amplitude. This will also relax the requirements for lowpass reconstruction filter at the DAC output.