AD9387 (evaluation board) cannot load data into register(s)

Hi,

The sequence to generate a 100Hz sine wave at 16MHz is correct.
The DDS uses SPI mode 2 that is CPOL = 1 and CPHA = 0 is that the CLK outside the SPI frame is high level and that the data will be on the first clock edge.

In the image I can't see the times but make sure that the minimum times are satisfied, Table 2 in the DS: AD9837 (Rev. A) (analog.com).

The last sequence is fine but if you do not want to continue loading frequencies in two consecutive writes, the command would only be 0x0000 (exit reset). 0x2000 means that you want to continue loading frequencies in two writes and also exit reset.

Thanks!

Hi,

The sequence to generate a 100Hz sine wave at 16MHz is correct.
The DDS uses SPI mode 2 that is CPOL = 1 and CPHA = 0 is that the CLK outside the SPI frame is high level and that the data will be on the first clock edge.

In the image I can't see the times but make sure that the minimum times are satisfied, Table 2 in the DS: AD9837 (Rev. A) (analog.com).

The last sequence is fine but if you do not want to continue loading frequencies in two consecutive writes, the command would only be 0x0000 (exit reset). 0x2000 means that you want to continue loading frequencies in two writes and also exit reset.

Thanks!

Hi,

Thank you for your helpful response. I forgot to mention that I've implemented SPI via bit banging. One clock period is 2ms.

I made some adjustments and the device seems to react to the reset (0x2100) command, but unfortunately I don't see a change in the frequency. All I get is a 516KHz sine, no matter what frequency I try.

I was wondering if I'm using FSYNC correctly? IIRC it can be held down for multiple words.

Full command

Start of commands

End of commands

I went ahead and tested with proper SPI instead of bit banging. The results are similar.

Hi,

FSYNC can be kept low for a multiple of 16 SCLK pulses and then brought high at the end of the data transfer. In this way, a continuous stream of 16-bit words can be loaded while FSYNC is held low; FSYNC goes high only after the 16th SCLK falling edge of the last word loaded.

I see something strange in the sending of the first frame (0x2100).The first frame which is the one that enables two consecutive writes to the frequency register and sets the reset to 1, does not appear to be sending 0x2100 it appears to be 0x0084, it looks like those bits have been shifted.I noticed that the same thing happens with the values you want to send in the SDATA, it looks like the data is being sent out.

I send you an example where I write in the same frame the configuration to obtain a sine wave at 516KHz.

The output is

Argh, I thought I checked it was correct... Oh well. That fixed it! Thank you!!