I'm using an AD9850 with a Xilinx Zynq-7020 FPGA SoC.
I want to be able to drive this via some form of SPI IP core (i.e. AXI SPI), or possibly the AXI SPI Engine.
However, the AD9850 does not use standard SPI:
- The CS logic is inverted (not a major problem, can invert in hardware).
- The device requires the LSB to be sent first (not a major problem, can invert in software).
- The serial input requires a 40-bit word (a major problem as AXI SPI only supports 8, 16, 32).
There is a staging IIO driver available for an old version of Linux, which is designed to work with an SPI peripheral.
What would be the best way for me to interface with this device, please? Should I make my own modified SPI IP core, or use the SPI Engine - if so, how do I set this up please?