AD9850 - SPI Interface and IIO Driver for Xilinx Zynq-7020

Hi AdamWilsonCPI ,

I may not be as familiar to your suggested AXI SPI engine. But I may agree with you that AD9850 does not somehow use the standard SPI as this was released many years ago. As for the linux driver you found, I may not be able to support it as well as the original programmers that developed this might not be with ADI right now. 

For SPI control, 

Note, the AD9851 has two 40-bit input registers. W_CLK and D7 is used program the first 40 bit register (or buffer) contents and a FQ_UD transfers the contents of the first register the second register where data becomes active.

Here's the sequence:

1) Apply power and REF CLK source to pin 9.

2) Send a master reset pulse. (this places the device in default state and the part is in parallel mode)

3) Send one W_CLK pulse, then send one FQ_UD (this places the device in serial mode)

4) Using W-CLK and D7 load 40 zeros first and then send one FQ_UD.

5) Now using W_CLK and D7 load the next forty bits with your desired FTW setting and then send one FQ_UD. The correct frequency should be at the output.

For other FTWs repeat step 5 only.

Note, you must always control the number of W_CLKs else the serial port will get out sequence.

All the best,

Jules

Hi AdamWilsonCPI ,

I may not be as familiar to your suggested AXI SPI engine. But I may agree with you that AD9850 does not somehow use the standard SPI as this was released many years ago. As for the linux driver you found, I may not be able to support it as well as the original programmers that developed this might not be with ADI right now. 

For SPI control, 

Note, the AD9851 has two 40-bit input registers. W_CLK and D7 is used program the first 40 bit register (or buffer) contents and a FQ_UD transfers the contents of the first register the second register where data becomes active.

Here's the sequence:

1) Apply power and REF CLK source to pin 9.

2) Send a master reset pulse. (this places the device in default state and the part is in parallel mode)

3) Send one W_CLK pulse, then send one FQ_UD (this places the device in serial mode)

4) Using W-CLK and D7 load 40 zeros first and then send one FQ_UD.

5) Now using W_CLK and D7 load the next forty bits with your desired FTW setting and then send one FQ_UD. The correct frequency should be at the output.

For other FTWs repeat step 5 only.

Note, you must always control the number of W_CLKs else the serial port will get out sequence.

All the best,

Jules

Hi Jules,

Thanks for the information!

I have managed to implement an IIO driver to work with Linux on the Zynq SoC, using an AXI SPI IP core peripheral to control the data and clock input lines, and an AXI GPIO IP core peripheral to control the FQ_UPDATE input line.

The driver works fine when I write a raw value to the IIO device, but the default frequency/phase values that I set during the startup probe do not seem to show on the output of the AD9850 - it just outputs seemingly random frequencies.

As part of the probe, I load the shift register with zeroes before sending the default data.

I have also tried to write default data multiple times during the probe, but the output still doesn't seem to change.

Does there need to be a delay between setting up the shift register and writing the initial data? What does this delay need to be?

Many thanks,

Adam