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generate Sinc pulse with AD9915 and FPGA

Category: Software
Product Number: AD9915

Hello everybody,

 I need to generate sinc pulse with FPGA and AD9915, I wanna know what can do for taking sinc pulse like the picture below.

Thank you.

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  • Hi  ,

    Apologies for overlooking this thread. I moved this from Clocks and Timing forum to Direct Digital Synthesis (DDS) forum. I was able to consult one of the expert of this product and yes it…

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  • Hi  ,

    Apologies for overlooking this thread. I moved this from Clocks and Timing forum to Direct Digital Synthesis (DDS) forum. I was able to consult one of the expert of this product and yes it is possible to generate a sinc pulse or any pulse at all it's just that you have to be clever in properly employing various resources. .

    Sinc pulses are a possibility, but only through the Parallel Data Port (PDP). Here’s how…

    1. Enable cosine (CFR1[16]=0)
    2. Enable OSK (CFR1[8]=1)
    3. Enable profile mode (CFR2[23]=1)
    4. Program Profile x for FTW=0 (0Hz)
    5. Set the PS[2:0] pins to select Profile x
    6. Disable profile mode (CFR2[23]=0)
    7. Enable streaming (CFR1[17]=1)  ç (optional)
    8. Enable PDP mode (CFR2[22]=1)
    9. Set F[3:0]=0100 (modulate phase/amplitude)

     

    Item 1 is necessary to produce a full scale amplitude value when fOUT=0Hz (assuming 0 phase). Item 4 establishes the 0Hz condition. The 0 phase condition is covered later. Note, the phase offset word in Profile x is immaterial, because profile mode is disabled in Item 6. Using the PDP with F[3:0]=0100 (phase/amplitude) means that the only purpose of Profile x is to provide the desired carrier frequency (0Hz in this case).

    At this point, the AD9915 acts as though it were nothing more than a 12-bit DAC, with D[11:0] being the DAC input. The DAC sample rate is fSYCN_CLK. So, you must write data to the PDP at the SYNC_CLK rate (a consequence of streaming mode). Assuming the 12-bit samples map out a time series of sinc amplitude values, the DAC output will be a sampled sinc waveform.

    However, there is still an additional requirement. The PDP is 32-bits wide and D[31:16] are phase bits when F[3:0]=0100. Therefore, you must be sure that D[31:16]=0x00 when sending the amplitude data (D[11:0]) over the 32-bit bus. Note, D[15:12] are “don’t care”.

    Item 7 is optional. That is, the user could disable streaming. However, this makes the PDP data dependent on IO_UPDATE. Using IO_UPDATE does not lend itself well to generating amplitude samples equally spaced in time. That’s the reason streaming was designed in as a feature.

    All the best,

    Jules

  • Hi Jules,

    Thank you for your answer, Actually, I solved this problem four days ago with one of my friends. Thank you for your answer 10000 times.

    Best Regards.

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